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spi-nor: spi-nor-ids: Add entries for mt25q variants
authorVignesh Raghavendra <vigneshr@ti.com>
Fri, 11 Oct 2019 07:58:19 +0000 (13:28 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Thu, 24 Oct 2019 19:18:32 +0000 (00:48 +0530)
commit8651593a8ce0c0599c993d76d2a927b125175cef
tree44f33fa7505061b547d8ee317dd673b9ec691509tree | snapshot
parentd66e07cdf9ab6f84ce121009b08860261bca7df2commit | diff
spi-nor: spi-nor-ids: Add entries for mt25q variants

mt25q* flashes support stateless 4 byte addressing opcodes. Add entries
for the same. These flashes have bit 6 set in 5th byte of READ ID
response when compared to n25q* variants.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
drivers/mtd/spi/spi-nor-ids.c diff | blob | history
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