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driver/ddr/fsl: Update DDR4 MR6 for Vref range
authorYork Sun <yorksun@freescale.com>
Wed, 4 Nov 2015 18:03:18 +0000 (10:03 -0800)
committerYork Sun <yorksun@freescale.com>
Mon, 14 Dec 2015 02:27:27 +0000 (18:27 -0800)
commit0fb7197436378eeb92ff8e2c6a6f6490b31eef1c
tree827a9d0417f2b47790dedd4ebebaa68383d5219ftree | snapshot
parent19601dd99c8169e27457a96f03f0c3fef908a4c6commit | diff
driver/ddr/fsl: Update DDR4 MR6 for Vref range

MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun <yorksun@freescale.com>
drivers/ddr/fsl/ctrl_regs.c diff | blob | history
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