X-Git-Url: https://git.librecmc.org/?p=oweals%2Fu-boot.git;a=blobdiff_plain;f=drivers%2Fnet%2Ffec_mxc.h;h=659d62646f8b4398c5d68b69c7ddb35d0caa7e65;hp=6cb1bfc055e620a355b9cd590c9cbb6aba0ca4f5;hb=89b5bd54c1a425e416d67ce21b0fd5fd7da6a1d4;hpb=0b23fb368d08c9669fac647971ff249c3f9fee8f diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 6cb1bfc055..659d62646f 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd * (C) Copyright 2008 Armadeus Systems, nc @@ -10,37 +11,18 @@ * * This file is based on mpc4200fec.h * (C) Copyright Motorola, Inc., 2000 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * */ - #ifndef __FEC_MXC_H #define __FEC_MXC_H -/** - * Layout description of the FEC - */ -struct ethernet_regs { - -/* [10:2]addr = 00 */ +#include -/* Control and status Registers (offset 000-1FF) */ +/* Layout description of the FEC */ +struct ethernet_regs { + /* [10:2]addr = 00 */ + /* Control and status Registers (offset 000-1FF) */ uint32_t res0[1]; /* MBAR_ETH + 0x000 */ uint32_t ievent; /* MBAR_ETH + 0x004 */ uint32_t imask; /* MBAR_ETH + 0x008 */ @@ -83,8 +65,7 @@ struct ethernet_regs { uint32_t emrbr; /* MBAR_ETH + 0x188 */ uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */ -/* MIB COUNTERS (Offset 200-2FF) */ - + /* MIB COUNTERS (Offset 200-2FF) */ uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */ uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */ uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ @@ -145,9 +126,17 @@ struct ethernet_regs { uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */ uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ - uint32_t res14[6]; /* MBAR_ETH + 0x2E4-2FC */ + uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) + uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ + uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ + uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ + uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */ + uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */ +#else uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */ +#endif }; #define FEC_IEVENT_HBERR 0x80000000 @@ -178,7 +167,6 @@ struct ethernet_regs { #define FEC_IMASKT_RL 0x00100000 #define FEC_IMASK_UN 0x00080000 - #define FEC_RCNTRL_MAX_FL_SHIFT 16 #define FEC_RCNTRL_LOOP 0x00000001 #define FEC_RCNTRL_DRT 0x00000002 @@ -186,6 +174,9 @@ struct ethernet_regs { #define FEC_RCNTRL_PROM 0x00000008 #define FEC_RCNTRL_BC_REJ 0x00000010 #define FEC_RCNTRL_FCE 0x00000020 +#define FEC_RCNTRL_RGMII 0x00000040 +#define FEC_RCNTRL_RMII 0x00000100 +#define FEC_RCNTRL_RMII_10T 0x00000200 #define FEC_TCNTRL_GTS 0x00000001 #define FEC_TCNTRL_HBC 0x00000002 @@ -195,22 +186,35 @@ struct ethernet_regs { #define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */ #define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */ - -/** - * @brief Descriptor buffer alignment - * - * i.MX27 requires a 16 byte alignment (but for the first element only) - */ -#define DB_ALIGNMENT 16 - -/** - * @brief Data buffer alignment - * - * i.MX27 requires a four byte alignment for transmit and 16 bits - * alignment for receive so take 16 - * Note: Valid for member data_pointer in struct buffer_descriptor - */ -#define DB_DATA_ALIGNMENT 16 +#define FEC_ECNTRL_SPEED 0x00000020 +#define FEC_ECNTRL_DBSWAP 0x00000100 +#define FEC_ECNTRL_TXC_DLY 0x00010000 /* TXC delayed */ +#define FEC_ECNTRL_RXC_DLY 0x00020000 /* RXC delayed */ + +#define FEC_X_WMRK_STRFWD 0x00000100 + +#define FEC_X_DES_ACTIVE_TDAR 0x01000000 +#define FEC_R_DES_ACTIVE_RDAR 0x01000000 + +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) +/* defines for MIIGSK */ +/* RMII frequency control: 0=50MHz, 1=5MHz */ +#define MIIGSK_CFGR_FRCONT (1 << 6) +/* loopback mode */ +#define MIIGSK_CFGR_LBMODE (1 << 4) +/* echo mode */ +#define MIIGSK_CFGR_EMODE (1 << 3) +/* MII gasket mode field */ +#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0) +/* MMI/7-Wire mode */ +#define MIIGSK_CFGR_IF_MODE_MII (0 << 0) +/* RMII mode */ +#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0) +/* reflects MIIGSK Enable bit (RO) */ +#define MIIGSK_ENR_READY (1 << 2) +/* enable MIGSK (set by default) */ +#define MIIGSK_ENR_EN (1 << 1) +#endif /** * @brief Receive & Transmit Buffer Descriptor definitions @@ -223,18 +227,16 @@ struct fec_bd { uint32_t data_pointer; /* payload's buffer address */ }; -/** - * Supported phy types on this platform - */ +/* Supported phy types on this platform */ enum xceiver_type { SEVENWIRE, /* 7-wire */ MII10, /* MII 10Mbps */ - MII100 /* MII 100Mbps */ + MII100, /* MII 100Mbps */ + RMII, /* RMII */ + RGMII, /* RGMII */ }; -/** - * @brief i.MX27-FEC private structure - */ +/* @brief i.MX27-FEC private structure */ struct fec_priv { struct ethernet_regs *eth; /* pointer to register'S base */ enum xceiver_type xcv_type; /* transceiver type */ @@ -243,8 +245,33 @@ struct fec_priv { struct fec_bd *tbd_base; /* TBD ring */ int tbd_index; /* next transmit BD to write */ bd_t *bd; - void *rdb_ptr; - void *base_ptr; + uint8_t *tdb_ptr; + int dev_id; + struct mii_dev *bus; +#ifdef CONFIG_PHYLIB + struct phy_device *phydev; + ofnode phy_of_node; +#else + int phy_id; + int (*mii_postcall)(int); +#endif +#ifdef CONFIG_DM_REGULATOR + struct udevice *phy_supply; +#endif +#if CONFIG_IS_ENABLED(DM_GPIO) + struct gpio_desc phy_reset_gpio; + uint32_t reset_delay; + uint32_t reset_post_delay; +#endif +#ifdef CONFIG_DM_ETH + u32 interface; +#endif + struct clk ipg_clk; + struct clk ahb_clk; + struct clk clk_enet_out; + struct clk clk_ref; + struct clk clk_ptp; + u32 clk_rate; }; /**