X-Git-Url: https://git.librecmc.org/?p=oweals%2Fu-boot.git;a=blobdiff_plain;f=board%2Fwandboard%2Fwandboard.c;h=69cdf3e9c96b18b7d15ac77816bc7faeb55c6ebb;hp=4ce74cd9715f2de86ea8b2ccb939534d7857dda6;hb=9fb625ce05539fe6876a59ce1dcadb76b33c6f6e;hpb=a187559e3d586891c917279044c5386d1b2adc6e diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 4ce74cd971..69cdf3e9c9 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -1,10 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2013 Freescale Semiconductor, Inc. * Copyright (C) 2014 O.S. Systems Software LTDA. * * Author: Fabio Estevam - * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -15,20 +14,21 @@ #include #include #include -#include -#include -#include -#include +#include +#include +#include +#include +#include #include +#include #include #include -#include -#include #include #include #include -#include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -36,10 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -47,11 +43,21 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) -#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) +#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13) #define REV_DETECTION IMX_GPIO_NR(2, 28) +/* Speed defined in Kconfig is only applicable when not using DM_I2C. */ +#ifdef CONFIG_DM_I2C +#define I2C1_SPEED_NON_DM 0 +#define I2C2_SPEED_NON_DM 0 +#else +#define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED +#define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED +#endif + +static bool with_pmic; + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -64,28 +70,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; -static iomux_v3_cfg_t const usdhc1_pads[] = { - IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* Carrier MicroSD Card Detect */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* SOM MicroSD Card Detect */ - IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), @@ -106,6 +90,11 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; +static iomux_v3_cfg_t const enet_ar8035_power_pads[] = { + /* AR8035 POWER */ + IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + static iomux_v3_cfg_t const rev_detection_pad[] = { IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; @@ -119,71 +108,58 @@ static void setup_iomux_enet(void) { SETUP_IOMUX_PADS(enet_pads); + if (with_pmic) { + SETUP_IOMUX_PADS(enet_ar8035_power_pads); + /* enable AR8035 POWER */ + gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER"); + gpio_direction_output(ETH_PHY_AR8035_POWER, 0); + } + /* wait until 3.3V of PHY and clock become stable */ + mdelay(10); + /* Reset AR8031 PHY */ + gpio_request(ETH_PHY_RESET, "PHY_RESET"); gpio_direction_output(ETH_PHY_RESET, 0); mdelay(10); gpio_set_value(ETH_PHY_RESET, 1); udelay(100); } -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) +static int ar8031_phy_fixup(struct phy_device *phydev) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - } + unsigned short val; + int mask; + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + if (with_pmic) + mask = 0xffe7; /* AR8035 */ + else + mask = 0xffe3; /* AR8031 */ + + val &= mask; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - return ret; + return 0; } -int board_mmc_init(bd_t *bis) +int board_phy_config(struct phy_device *phydev) { - int ret; - u32 index = 0; - - /* - * Following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 SOM MicroSD - * mmc1 Carrier board MicroSD - */ - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 4; - gpio_direction_input(USDHC3_CD_GPIO); - break; - case 1: - SETUP_IOMUX_PADS(usdhc1_pads); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - usdhc_cfg[1].max_bus_width = 4; - gpio_direction_input(USDHC1_CD_GPIO); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } + ar8031_phy_fixup(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); return 0; } @@ -223,6 +199,40 @@ struct i2c_pads_info mx6dl_i2c2_pad_info = { } }; +struct i2c_pads_info mx6q_i2c3_pad_info = { + .scl = { + .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(7, 11) + } +}; + +struct i2c_pads_info mx6dl_i2c3_pad_info = { + .scl = { + .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(7, 11) + } +}; + static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = { IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */ @@ -258,14 +268,29 @@ static void do_enable_hdmi(struct display_info_t const *dev) static int detect_i2c(struct display_info_t const *dev) { +#ifdef CONFIG_DM_I2C + struct udevice *bus, *udev; + int rc; + + rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus); + if (rc) + return rc; + rc = dm_i2c_probe(bus, dev->addr, 0, &udev); + if (rc) + return 0; + return 1; +#else return (0 == i2c_set_bus_num(dev->bus)) && (0 == i2c_probe(dev->addr)); +#endif } static void enable_fwadapt_7wvga(struct display_info_t const *dev) { SETUP_IOMUX_PADS(fwadapt_7wvga_pads); + gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN"); + gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN"); gpio_direction_output(IMX_GPIO_NR(2, 10), 1); gpio_direction_output(IMX_GPIO_NR(2, 11), 1); } @@ -328,6 +353,7 @@ static void setup_display(void) /* Disable LCD backlight */ SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20); + gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN"); gpio_direction_input(IMX_GPIO_NR(4, 20)); } #endif /* CONFIG_VIDEO_IPUV3 */ @@ -342,9 +368,41 @@ int board_eth_init(bd_t *bis) int board_early_init_f(void) { setup_iomux_uart(); -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); +#ifdef CONFIG_SATA + setup_sata(); #endif + + return 0; +} + +#define PMIC_I2C_BUS 2 + +int power_init_board(void) +{ + struct udevice *dev; + int reg, ret; + + puts("PMIC: "); + + ret = pmic_get("pfuze100", &dev); + if (ret < 0) { + printf("pmic_get() ret %d\n", ret); + return 0; + } + + reg = pmic_reg_read(dev, PFUZE100_DEVICEID); + if (reg < 0) { + printf("pmic_reg_read() ret %d\n", reg); + return 0; + } + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + with_pmic = true; + + /* Set VGEN2 to 1.5V and enable */ + reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | (1 << (LDO_EN))); + pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg); return 0; } @@ -377,6 +435,14 @@ static bool is_revc1(void) return false; } +static bool is_revd1(void) +{ + if (with_pmic) + return true; + else + return false; +} + int board_late_init(void) { #ifdef CONFIG_CMD_BMODE @@ -384,15 +450,19 @@ int board_late_init(void) #endif #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) - setenv("board_rev", "MX6Q"); + if (is_mx6dqp()) + env_set("board_rev", "MX6QP"); + else if (is_mx6dq()) + env_set("board_rev", "MX6Q"); else - setenv("board_rev", "MX6DL"); + env_set("board_rev", "MX6DL"); - if (is_revc1()) - setenv("board_name", "C1"); + if (is_revd1()) + env_set("board_name", "D1"); + else if (is_revc1()) + env_set("board_name", "C1"); else - setenv("board_name", "B1"); + env_set("board_name", "B1"); #endif return 0; } @@ -402,21 +472,50 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); - else - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); +#if defined(CONFIG_VIDEO_IPUV3) + setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info); + if (is_mx6dq() || is_mx6dqp()) { + setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info); + setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info); + } else { + setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info); + setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info); + } + + setup_display(); +#endif return 0; } int checkboard(void) { - if (is_revc1()) + gpio_request(REV_DETECTION, "REV_DETECT"); + + if (is_revd1()) + puts("Board: Wandboard rev D1\n"); + else if (is_revc1()) puts("Board: Wandboard rev C1\n"); else puts("Board: Wandboard rev B1\n"); return 0; } + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (is_mx6dq()) { + if (!strcmp(name, "imx6q-wandboard-revb1")) + return 0; + } else if (is_mx6dqp()) { + if (!strcmp(name, "imx6qp-wandboard-revd1")) + return 0; + } else if (is_mx6dl() || is_mx6solo()) { + if (!strcmp(name, "imx6dl-wandboard-revb1")) + return 0; + } + + return -EINVAL; +} +#endif