X-Git-Url: https://git.librecmc.org/?p=oweals%2Fu-boot.git;a=blobdiff_plain;f=board%2Fsbc8349%2Fsbc8349.c;h=1e3529f3348b668e438d30ea9d6daa17c426f98e;hp=4154f29d8cd948ad38f53aa2c5f45035c51603ae;hb=358b6f72c28c80699536f7137063095116e1675e;hpb=6d0f6bcf337c5261c08fabe12982178c2c489d76 diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 4154f29d8c..1e3529f334 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -1,45 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * sbc8349.c -- WindRiver SBC8349 board support. * Copyright (c) 2006-2007 Wind River Systems, Inc. * * Paul Gortmaker * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * */ #include +#include +#include #include #include +#include #include #include #include #include #if defined(CONFIG_OF_LIBFDT) -#include +#include #endif +#include + +DECLARE_GLOBAL_DATA_PTR; int fixed_sdram(void); void sdram_init(void); -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) void ddr_enable_ecc(unsigned int dram_size); #endif @@ -52,7 +40,7 @@ int board_early_init_f (void) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) -phys_size_t initdram (int board_type) +int dram_init(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; @@ -61,7 +49,7 @@ phys_size_t initdram (int board_type) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else @@ -78,8 +66,10 @@ phys_size_t initdram (int board_type) */ ddr_enable_ecc(msize * 1024 * 1024); #endif - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); + /* set total bus SDRAM size(bytes) -- DDR */ + gd->ram_size = msize * 1024 * 1024; + + return 0; } #if !defined(CONFIG_SPD_EEPROM) @@ -89,26 +79,25 @@ phys_size_t initdram (int board_type) int fixed_sdram(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; /* DDR size in bytes */ + u32 ddr_size_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif - im->ddr.csbnds[2].csbnds = 0x0000000f; - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG; + +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[2].csbnds = + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; /* currently we use only one CS, so disable the other banks */ im->ddr.cs_config[0] = 0; @@ -160,8 +149,11 @@ int checkboard (void) void sdram_init(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile lbus83xx_t *lbc= &immap->lbus; + volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; + const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | + LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | + LSDMR_WRC3 | LSDMR_CL3; puts("\n SDRAM on Local Bus: "); print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); @@ -171,22 +163,27 @@ void sdram_init(void) */ /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->lbcr = 0x00000000; + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; + /* LB sdram refresh timer, about 6us */ + lbc->lsrt = 0x32000000; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + /* 0x68636733; precharge all the banks */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + /* 0x48636733; auto refresh */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; asm("sync"); /*1 times*/ *sdram_addr = 0xff; @@ -214,12 +211,13 @@ void sdram_init(void) udelay(100); /* 0x58636733; mode register write operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; + lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; asm("sync"); *sdram_addr = 0xff; udelay(100); @@ -232,11 +230,13 @@ void sdram_init(void) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif