X-Git-Url: https://git.librecmc.org/?p=oweals%2Fu-boot.git;a=blobdiff_plain;f=board%2FCarMediaLab%2Fflea3%2Fflea3.c;h=61d965f5f65ac6963f379c3a7be8956a28106658;hp=6cef24c76f3758cb6029d270024851facde837c8;hb=c27178ba3649f539c9f1890ea147f4c5415f63b5;hpb=34a31bf52b83fd689c414f54eab2f263b5f5383d diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c index 6cef24c76f..61d965f5f6 100644 --- a/board/CarMediaLab/flea3/flea3.c +++ b/board/CarMediaLab/flea3/flea3.c @@ -1,41 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2007, Guennadi Liakhovetski * * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. * * Copyright (C) 2011, Stefano Babic - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA */ #include +#include #include -#include +#include +#include +#include #include #include -#include -#include +#include #include #include #include #include #include +#include +#include +#include #ifndef CONFIG_BOARD_EARLY_INIT_F #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" @@ -44,18 +32,6 @@ #define CCM_CCMR_CONFIG 0x003F4208 #define ESDCTL_DDR2_CONFIG 0x007FFC3F -#define ESDCTL_0x92220000 0x92220000 -#define ESDCTL_0xA2220000 0xA2220000 -#define ESDCTL_0xB2220000 0xB2220000 -#define ESDCTL_0x82228080 0x82228080 -#define ESDCTL_DDR2_EMR2 0x04000000 -#define ESDCTL_DDR2_EMR3 0x06000000 -#define ESDCTL_PRECHARGE 0x00000400 -#define ESDCTL_DDR2_EN_DLL 0x02000400 -#define ESDCTL_DDR2_RESET_DLL 0x00000333 -#define ESDCTL_DDR2_MR 0x00000233 -#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 -#define ESDCTL_DELAY_LINE5 0x00F49F00 static inline void dram_wait(unsigned int count) { @@ -75,83 +51,6 @@ int dram_init(void) return 0; } -static void board_setup_sdram_bank(u32 start_address) - -{ - struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; - u32 *cfg_reg, *ctl_reg; - u32 val; - - switch (start_address) { - case CSD0_BASE_ADDR: - cfg_reg = &esdc->esdcfg0; - ctl_reg = &esdc->esdctl0; - break; - case CSD1_BASE_ADDR: - cfg_reg = &esdc->esdcfg1; - ctl_reg = &esdc->esdctl1; - break; - default: - return; - } - - /* Initialize MISC register for DDR2 */ - val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST | - ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN; - writel(val, &esdc->esdmisc); - val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST); - writel(val, &esdc->esdmisc); - - /* - * according to DDR2 specs, wait a while before - * the PRECHARGE_ALL command - */ - dram_wait(0x20000); - - /* Load DDR2 config and timing */ - writel(ESDCTL_DDR2_CONFIG, cfg_reg); - - /* Precharge ALL */ - writel(ESDCTL_0x92220000, - ctl_reg); - writel(0xda, start_address + ESDCTL_PRECHARGE); - - /* Load mode */ - writel(ESDCTL_0xB2220000, - ctl_reg); - writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */ - writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */ - writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ - writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */ - - /* Precharge ALL */ - writel(ESDCTL_0x92220000, - ctl_reg); - writel(0xda, start_address + ESDCTL_PRECHARGE); - - /* Set mode auto refresh : at least two refresh are required */ - writel(ESDCTL_0xA2220000, - ctl_reg); - writel(0xda, start_address); - writel(0xda, start_address); - - writel(ESDCTL_0xB2220000, - ctl_reg); - writeb(0xda, start_address + ESDCTL_DDR2_MR); - writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT); - - /* OCD mode exit */ - writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ - - /* Set normal mode */ - writel(ESDCTL_0x82228080, - ctl_reg); - - dram_wait(0x20000); - - /* Do not set delay lines, only for MDDR */ -} - static void board_setup_sdram(void) { struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; @@ -160,67 +59,77 @@ static void board_setup_sdram(void) writel(0x2000, &esdc->esdctl0); writel(0x2000, &esdc->esdctl1); - board_setup_sdram_bank(CSD0_BASE_ADDR); + + mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, + 13, 10, 2, 0x8080); } static void setup_iomux_uart3(void) { - mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7); - mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7); + static const iomux_v3_cfg_t uart3_pads[] = { + MX35_PAD_RTS2__UART3_RXD_MUX, + MX35_PAD_CTS2__UART3_TXD_MUX, + }; + + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); } +#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) + static void setup_iomux_i2c(void) { - int pad; - - mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); - - pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ - | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); + static const iomux_v3_cfg_t i2c_pads[] = { + NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), - mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); - mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); + NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL), + }; - mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1); - mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1); - - mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad); - mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad); + imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); } static void setup_iomux_spi(void) { - mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); + static const iomux_v3_cfg_t spi_pads[] = { + MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, + MX35_PAD_CSPI1_MISO__CSPI1_MISO, + MX35_PAD_CSPI1_SS0__CSPI1_SS0, + MX35_PAD_CSPI1_SS1__CSPI1_SS1, + MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, + }; + + imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); } static void setup_iomux_fec(void) { - /* setup pins for FEC */ - mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + static const iomux_v3_cfg_t fec_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + /* GPIO used to power off ethernet */ + MX35_PAD_STXFS4__GPIO2_31, + }; + /* setup pins for FEC */ + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } int board_early_init_f(void) @@ -229,7 +138,7 @@ int board_early_init_f(void) (struct ccm_regs *)IMX_CCM_BASE; /* setup GPIO3_1 to set HighVCore signal */ - mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5); + imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1); gpio_direction_output(65, 1); /* initialize PLL and clock configuration */ @@ -278,6 +187,11 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + /* Enable power for ethernet */ + gpio_direction_output(63, 0); + + udelay(2000); + return 0; } @@ -287,3 +201,24 @@ u32 get_board_rev(void) return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; } + +/* + * called prior to booting kernel or by 'fdt boardsetup' command + * + */ +int ft_board_setup(void *blob, bd_t *bd) +{ + static const struct node_info nodes[] = { + { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */ + { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + }; + + if (env_get("fdt_noauto")) { + puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); + return 0; + } + + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + + return 0; +}