X-Git-Url: https://git.librecmc.org/?p=oweals%2Fu-boot.git;a=blobdiff_plain;f=arch%2Farm%2Fmach-imx%2Fimx8m%2Fsoc.c;h=8b6be7bc1996d28a7f9604b8e5f5052b95495ac2;hp=11251c5f9ad98184bd415513c4917c2006d4a621;hb=a07bcec403a22f6b848cff06c8094f1da7bc23e1;hpb=cd357ad112326d07b7cc3f0a96aef6752ce74574

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 11251c5f9a..8b6be7bc19 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -14,6 +15,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/syscounter.h>
 #include <asm/armv8/mmu.h>
+#include <dm/uclass.h>
 #include <errno.h>
 #include <fdt_support.h>
 #include <fsl_wdog.h>
@@ -21,7 +23,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SECURE_BOOT)
+#if defined(CONFIG_IMX_HAB)
 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
 	.bank = 1,
 	.word = 3,
@@ -55,6 +57,14 @@ void enable_tzc380(void)
 	/* Enable TZASC and lock setting */
 	setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
 	setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
+	if (is_imx8mm() || is_imx8mn() || is_imx8mp())
+		setbits_le32(&gpr->gpr[10], BIT(1));
+	/*
+	 * set Region 0 attribute to allow secure and non-secure
+	 * read/write permission. Found some masters like usb dwc3
+	 * controllers can't work with secure memory.
+	 */
+	writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
 }
 
 void set_wdog_reset(struct wdog_regs *wdog)
@@ -112,16 +122,18 @@ static struct mm_region imx8m_mem_map[] = {
 		/* DRAM1 */
 		.virt = 0x40000000UL,
 		.phys = 0x40000000UL,
-		.size = 0xC0000000UL,
+		.size = PHYS_SDRAM_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_OUTER_SHARE
+#ifdef PHYS_SDRAM_2_SIZE
 	}, {
 		/* DRAM2 */
 		.virt = 0x100000000UL,
 		.phys = 0x100000000UL,
-		.size = 0x040000000UL,
+		.size = PHYS_SDRAM_2_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_OUTER_SHARE
+#endif
 	}, {
 		/* List terminator */
 		0,
@@ -130,26 +142,115 @@ static struct mm_region imx8m_mem_map[] = {
 
 struct mm_region *mem_map = imx8m_mem_map;
 
+void enable_caches(void)
+{
+	/*
+	 * If OPTEE runs, remove OPTEE memory from MMU table to
+	 * avoid speculative prefetch. OPTEE runs at the top of
+	 * the first memory bank
+	 */
+	if (rom_pointer[1])
+		imx8m_mem_map[5].size -= rom_pointer[1];
+
+	icache_enable();
+	dcache_enable();
+}
+
+static u32 get_cpu_variant_type(u32 type)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[1];
+	struct fuse_bank1_regs *fuse =
+		(struct fuse_bank1_regs *)bank->fuse_regs;
+
+	u32 value = readl(&fuse->tester4);
+
+	if (type == MXC_CPU_IMX8MQ) {
+		if ((value & 0x3) == 0x2)
+			return MXC_CPU_IMX8MD;
+		else if (value & 0x200000)
+			return MXC_CPU_IMX8MQL;
+
+	} else if (type == MXC_CPU_IMX8MM) {
+		switch (value & 0x3) {
+		case 2:
+			if (value & 0x1c0000)
+				return MXC_CPU_IMX8MMDL;
+			else
+				return MXC_CPU_IMX8MMD;
+		case 3:
+			if (value & 0x1c0000)
+				return MXC_CPU_IMX8MMSL;
+			else
+				return MXC_CPU_IMX8MMS;
+		default:
+			if (value & 0x1c0000)
+				return MXC_CPU_IMX8MML;
+			break;
+		}
+	} else if (type == MXC_CPU_IMX8MN) {
+		switch (value & 0x3) {
+		case 2:
+			if (value & 0x1000000)
+				return MXC_CPU_IMX8MNDL;
+			else
+				return MXC_CPU_IMX8MND;
+		case 3:
+			if (value & 0x1000000)
+				return MXC_CPU_IMX8MNSL;
+			else
+				return MXC_CPU_IMX8MNS;
+		default:
+			if (value & 0x1000000)
+				return MXC_CPU_IMX8MNL;
+			break;
+		}
+	}
+
+	return type;
+}
+
 u32 get_cpu_rev(void)
 {
 	struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 	u32 reg = readl(&ana_pll->digprog);
 	u32 type = (reg >> 16) & 0xff;
+	u32 major_low = (reg >> 8) & 0xff;
 	u32 rom_version;
 
 	reg &= 0xff;
 
-	if (reg == CHIP_REV_1_0) {
-		/*
-		 * For B0 chip, the DIGPROG is not updated, still TO1.0.
-		 * we have to check ROM version further
-		 */
-		rom_version = readl((void __iomem *)ROM_VERSION_A0);
-		if (rom_version != CHIP_REV_1_0) {
-			rom_version = readl((void __iomem *)ROM_VERSION_B0);
-			if (rom_version >= CHIP_REV_2_0)
-				reg = CHIP_REV_2_0;
+	/* iMX8MP */
+	if (major_low == 0x43) {
+		return (MXC_CPU_IMX8MP << 12) | reg;
+	} else if (major_low == 0x42) {
+		/* iMX8MN */
+		type = get_cpu_variant_type(MXC_CPU_IMX8MN);
+	} else if (major_low == 0x41) {
+		type = get_cpu_variant_type(MXC_CPU_IMX8MM);
+	} else {
+		if (reg == CHIP_REV_1_0) {
+			/*
+			 * For B0 chip, the DIGPROG is not updated,
+			 * it is still TO1.0. we have to check ROM
+			 * version or OCOTP_READ_FUSE_DATA.
+			 * 0xff0055aa is magic number for B1.
+			 */
+			if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
+				reg = CHIP_REV_2_1;
+			} else {
+				rom_version =
+					readl((void __iomem *)ROM_VERSION_A0);
+				if (rom_version != CHIP_REV_1_0) {
+					rom_version = readl((void __iomem *)ROM_VERSION_B0);
+					rom_version &= 0xff;
+					if (rom_version == CHIP_REV_2_0)
+						reg = CHIP_REV_2_0;
+				}
+			}
 		}
+
+		type = get_cpu_variant_type(type);
 	}
 
 	return (type << 12) | reg;
@@ -167,8 +268,33 @@ static void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog3->wmcr);
 }
 
+int arch_cpu_init_dm(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (CONFIG_IS_ENABLED(CLK)) {
+		ret = uclass_get_device_by_name(UCLASS_CLK,
+						"clock-controller@30380000",
+						&dev);
+		if (ret < 0) {
+			printf("Failed to find clock node. Check device tree\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
 int arch_cpu_init(void)
 {
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	/*
+	 * ROM might disable clock for SCTR,
+	 * enable the clock before timer_init.
+	 */
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		clock_enable(CCGR_SCTR, 1);
 	/*
 	 * Init timer at very early state, because sscg pll setting
 	 * will use it
@@ -180,9 +306,63 @@ int arch_cpu_init(void)
 		imx_set_wdog_powerdown(false);
 	}
 
+	if (is_imx8mq()) {
+		clock_enable(CCGR_OCOTP, 1);
+		if (readl(&ocotp->ctrl) & 0x200)
+			writel(0x200, &ocotp->ctrl_clr);
+	}
+
 	return 0;
 }
 
+#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
+struct rom_api *g_rom_api = (struct rom_api *)0x980;
+
+enum boot_device get_boot_device(void)
+{
+	volatile gd_t *pgd = gd;
+	int ret;
+	u32 boot;
+	u16 boot_type;
+	u8 boot_instance;
+	enum boot_device boot_dev = SD1_BOOT;
+
+	ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+					  ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+	gd = pgd;
+
+	if (ret != ROM_API_OKAY) {
+		puts("ROMAPI: failure at query_boot_info\n");
+		return -1;
+	}
+
+	boot_type = boot >> 16;
+	boot_instance = (boot >> 8) & 0xff;
+
+	switch (boot_type) {
+	case BT_DEV_TYPE_SD:
+		boot_dev = boot_instance + SD1_BOOT;
+		break;
+	case BT_DEV_TYPE_MMC:
+		boot_dev = boot_instance + MMC1_BOOT;
+		break;
+	case BT_DEV_TYPE_NAND:
+		boot_dev = NAND_BOOT;
+		break;
+	case BT_DEV_TYPE_FLEXSPINOR:
+		boot_dev = QSPI_BOOT;
+		break;
+	case BT_DEV_TYPE_USB:
+		boot_dev = USB_BOOT;
+		break;
+	default:
+		break;
+	}
+
+	return boot_dev;
+}
+#endif
+
 bool is_usb_boot(void)
 {
 	return get_boot_device() == USB_BOOT;
@@ -227,16 +407,45 @@ int ft_system_setup(void *blob, bd_t *bd)
 }
 #endif
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
 void reset_cpu(ulong addr)
 {
-	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+       struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
 
-	/* Clear WDA to trigger WDOG_B immediately */
-	writew((WCR_WDE | WCR_SRS), &wdog->wcr);
+       if (!addr)
+	       wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 
-	while (1) {
-		/*
-		 * spin for .5 seconds before reset
-		 */
+       /* Clear WDA to trigger WDOG_B immediately */
+       writew((WCR_WDE | WCR_SRS), &wdog->wcr);
+
+       while (1) {
+               /*
+                * spin for .5 seconds before reset
+                */
+       }
+}
+#endif
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+static void acquire_buildinfo(void)
+{
+	u64 atf_commit = 0;
+
+	/* Get ARM Trusted Firmware commit id */
+	atf_commit = call_imx_sip(IMX_SIP_BUILDINFO,
+				  IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
+	if (atf_commit == 0xffffffff) {
+		debug("ATF does not support build info\n");
+		atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
 	}
+
+	printf("\n BuildInfo:\n  - ATF %s\n\n", (char *)&atf_commit);
 }
+
+int arch_misc_init(void)
+{
+	acquire_buildinfo();
+
+	return 0;
+}
+#endif