rename CFG_ macros to CONFIG_SYS

[oweals/u-boot.git] / post / lib_ppc / threex.c

diff --git a/post/lib_ppc/threex.c b/post/lib_ppc/threex.c
index 2c72063848e0560de9580534adce9328bfb0ca34..350a12ae78ca56726870078415d31e915df86fc9 100644 (file)
--- a/post/lib_ppc/threex.c
+++ b/post/lib_ppc/threex.c
@@ -35,12 +35,10 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CFG_POST_CPU
+#if CONFIG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
     ulong op2);
@@ -55,73 +53,73 @@ static struct cpu_post_threex_s
 } cpu_post_threex_table[] =
 {
     {
-       OP_OR,
+       OP_OR,
        0x1234,
        0x5678,
        0x1234 | 0x5678
     },
     {
-       OP_ORC,
+       OP_ORC,
        0x1234,
        0x5678,
        0x1234 | ~0x5678
     },
     {
-       OP_XOR,
+       OP_XOR,
        0x1234,
        0x5678,
        0x1234 ^ 0x5678
     },
     {
-       OP_NAND,
+       OP_NAND,
        0x1234,
        0x5678,
        ~(0x1234 & 0x5678)
     },
     {
-       OP_NOR,
+       OP_NOR,
        0x1234,
        0x5678,
        ~(0x1234 | 0x5678)
     },
     {
-       OP_EQV,
+       OP_EQV,
        0x1234,
        0x5678,
        ~(0x1234 ^ 0x5678)
     },
     {
-       OP_SLW,
+       OP_SLW,
        0x80,
        16,
        0x800000
     },
     {
-       OP_SLW,
+       OP_SLW,
        0x80,
        32,
        0
     },
     {
-       OP_SRW,
+       OP_SRW,
        0x800000,
        16,
        0x80
     },
     {
-       OP_SRW,
+       OP_SRW,
        0x800000,
        32,
        0
     },
     {
-       OP_SRAW,
+       OP_SRAW,
        0x80000000,
        3,
        0xf0000000
     },
     {
-       OP_SRAW,
+       OP_SRAW,
        0x8000,
        3,
        0x1000
@@ -146,7 +144,7 @@ int cpu_post_test_threex (void)
            unsigned int reg1 = (reg + 1) % 32;
            unsigned int reg2 = (reg + 2) % 32;
            unsigned int stk = reg < 16 ? 31 : 15;
-           unsigned long code[] =
+           unsigned long code[] =
            {
                ASM_STW(stk, 1, -4),
                ASM_ADDI(stk, 1, -24),
@@ -167,7 +165,7 @@ int cpu_post_test_threex (void)
                ASM_LWZ(stk, 1, -4),
                ASM_BLR,
            };
-           unsigned long codecr[] =
+           unsigned long codecr[] =
            {
                ASM_STW(stk, 1, -4),
                ASM_ADDI(stk, 1, -24),
@@ -193,26 +191,26 @@ int cpu_post_test_threex (void)
 
            if (ret == 0)
            {
-               cr = 0;
-               cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
+               cr = 0;
+               cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
 
-               ret = res == test->res && cr == 0 ? 0 : -1;
+               ret = res == test->res && cr == 0 ? 0 : -1;
 
-               if (ret != 0)
-               {
+               if (ret != 0)
+               {
                    post_log ("Error at threex test %d !\n", i);
-               }
+               }
            }
 
            if (ret == 0)
            {
-               cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
+               cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
 
-               ret = res == test->res &&
+               ret = res == test->res &&
                      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 
-               if (ret != 0)
-               {
+               if (ret != 0)
+               {
                    post_log ("Error at threex test %d !\n", i);
                }
            }
@@ -220,10 +218,9 @@ int cpu_post_test_threex (void)
     }
 
     if (flag)
-       enable_interrupts();
+       enable_interrupts();
 
     return ret;
 }
 
 #endif
-#endif