colibri_imx6: fix video stdout in default environment

[oweals/u-boot.git] / include / zynqpl.h

diff --git a/include/zynqpl.h b/include/zynqpl.h
index 0247ef61cce1354b336a711319f6cab058261be5..766e6918cd384c720ac19dbed4f152c61aa3b2d4 100644 (file)
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -1,26 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2012-2013, Xilinx, Michal Simek
  *
  * (C) Copyright 2012
  * Joe Hershberger <joe.hershberger@ni.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #ifndef _ZYNQPL_H_
@@ -28,32 +11,58 @@
 
 #include <xilinx.h>
 
-extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int zynq_info(Xilinx_desc *desc);
+#ifdef CONFIG_CMD_ZYNQ_AES
+int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen);
+#endif
 
-#define XILINX_ZYNQ_7010       0x2
-#define XILINX_ZYNQ_7020       0x7
-#define XILINX_ZYNQ_7030       0xc
-#define XILINX_ZYNQ_7045       0x11
+extern struct xilinx_fpga_op zynq_op;
+
+#define XILINX_ZYNQ_XC7Z007S   0x3
+#define XILINX_ZYNQ_XC7Z010    0x2
+#define XILINX_ZYNQ_XC7Z012S   0x1c
+#define XILINX_ZYNQ_XC7Z014S   0x8
+#define XILINX_ZYNQ_XC7Z015    0x1b
+#define XILINX_ZYNQ_XC7Z020    0x7
+#define XILINX_ZYNQ_XC7Z030    0xc
+#define XILINX_ZYNQ_XC7Z035    0x12
+#define XILINX_ZYNQ_XC7Z045    0x11
+#define XILINX_ZYNQ_XC7Z100    0x16
 
 /* Device Image Sizes */
+#define XILINX_XC7Z007S_SIZE   16669920/8
 #define XILINX_XC7Z010_SIZE    16669920/8
+#define XILINX_XC7Z012S_SIZE   28085344/8
+#define XILINX_XC7Z014S_SIZE   32364512/8
+#define XILINX_XC7Z015_SIZE    28085344/8
 #define XILINX_XC7Z020_SIZE    32364512/8
 #define XILINX_XC7Z030_SIZE    47839328/8
+#define XILINX_XC7Z035_SIZE    106571232/8
 #define XILINX_XC7Z045_SIZE    106571232/8
+#define XILINX_XC7Z100_SIZE    139330784/8
 
-/* Descriptor Macros */
-#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
-
-#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
-
-#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" }
+/* Device Names */
+#define XILINX_XC7Z007S_NAME   "7z007s"
+#define XILINX_XC7Z010_NAME    "7z010"
+#define XILINX_XC7Z012S_NAME   "7z012s"
+#define XILINX_XC7Z014S_NAME   "7z014s"
+#define XILINX_XC7Z015_NAME    "7z015"
+#define XILINX_XC7Z020_NAME    "7z020"
+#define XILINX_XC7Z030_NAME    "7z030"
+#define XILINX_XC7Z035_NAME    "7z035"
+#define XILINX_XC7Z045_NAME    "7z045"
+#define XILINX_XC7Z100_NAME    "7z100"
 
-#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
+#if defined(CONFIG_FPGA)
+#define ZYNQ_DESC(name) { \
+       .idcode = XILINX_ZYNQ_XC##name, \
+       .fpga_size = XILINX_XC##name##_SIZE, \
+       .devicename = XILINX_XC##name##_NAME \
+       }
+#else
+#define ZYNQ_DESC(name) { \
+       .idcode = XILINX_ZYNQ_XC##name, \
+       .devicename = XILINX_XC##name##_NAME \
+       }
+#endif
 
 #endif /* _ZYNQPL_H_ */