+/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * vsc9953.h
- *
- * Driver for the Vitesse VSC9953 L2 Switch
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013, 2015 Freescale Semiconductor, Inc.
*
+ * Driver for the Vitesse VSC9953 L2 Switch
*/
#ifndef _VSC9953_H_
/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
#define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
+/* Macros for vsc9953_sys_sys.stat_cfg register */
+#define VSC9953_STAT_CLEAR_RX 0x00000400
+#define VSC9953_STAT_CLEAR_TX 0x00000800
+#define VSC9953_STAT_CLEAR_DR 0x00001000
+
/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
#define VSC9953_VCAP_MV_CFG 0x0000ffff
#define VSC9953_VCAP_UPDATE_CTRL 0x01000004
+/* Macros for register vsc9953_ana_ana_tables.mac_access register */
+#define VSC9953_MAC_CMD_IDLE 0x00000000
+#define VSC9953_MAC_CMD_LEARN 0x00000001
+#define VSC9953_MAC_CMD_FORGET 0x00000002
+#define VSC9953_MAC_CMD_AGE 0x00000003
+#define VSC9953_MAC_CMD_NEXT 0x00000004
+#define VSC9953_MAC_CMD_READ 0x00000006
+#define VSC9953_MAC_CMD_WRITE 0x00000007
+#define VSC9953_MAC_CMD_MASK 0x00000007
+#define VSC9953_MAC_CMD_VALID 0x00000800
+#define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000
+#define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200
+#define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
+#define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
+#define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600
+#define VSC9953_MAC_DESTIDX_MASK 0x000001f8
+#define VSC9953_MAC_VID_MASK 0x1fff0000
+#define VSC9953_MAC_MACH_MASK 0x0000ffff
+
/* Macros for vsc9953_ana_port.vlan_cfg register */
#define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
#define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
+#define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000
+#define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000
#define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
/* Macros for vsc9953_rew_port.port_vlan_cfg register */
#define VSC9953_VLAN_CMD_WRITE 0x00000002
#define VSC9953_VLAN_CMD_INIT 0x00000003
+/* Macros for vsc9953_ana_port.port_cfg register */
+#define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
+#define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
+#define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
+#define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
+#define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c
+
/* Macros for vsc9953_qsys_sys.switch_port_mode register */
#define VSC9953_PORT_ENA 0x00002000
+/* Macros for vsc9953_ana_ana.agen_ctrl register */
+#define VSC9953_FID_MASK_ALL 0x00fff000
+
/* Macros for vsc9953_ana_ana.adv_learn register */
#define VSC9953_VLAN_CHK 0x00000400
+/* Macros for vsc9953_ana_ana.auto_age register */
+#define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe
+
/* Macros for vsc9953_rew_port.port_tag_cfg register */
#define VSC9953_TAG_CFG_MASK 0x00000180
#define VSC9953_TAG_CFG_NONE 0x00000000
#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
#define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
#define VSC9953_TAG_CFG_ALL 0x00000180
+#define VSC9953_TAG_VID_PVID 0x00000010
+
+/* Macros for vsc9953_ana_ana.anag_efil register */
+#define VSC9953_AGE_PORT_EN 0x00080000
+#define VSC9953_AGE_PORT_MASK 0x0007c000
+#define VSC9953_AGE_VID_EN 0x00002000
+#define VSC9953_AGE_VID_MASK 0x00001fff
+
+/* Macros for vsc9953_ana_ana_tables.mach_data register */
+#define VSC9953_MACHDATA_VID_MASK 0x1fff0000
+
+/* Macros for vsc9953_ana_common.aggr_cfg register */
+#define VSC9953_AC_RND_ENA 0x00000080
+#define VSC9953_AC_DMAC_ENA 0x00000040
+#define VSC9953_AC_SMAC_ENA 0x00000020
+#define VSC9953_AC_IP6_LBL_ENA 0x00000010
+#define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008
+#define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004
+#define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002
+#define VSC9953_AC_MASK 0x000000fe
+
+/* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
+#define VSC9953_PGID_PORT_MASK 0x000003ff
#define VSC9953_MAX_PORTS 10
#define VSC9953_PORT_CHECK(port) \
#define VSC9953_MAX_VLAN 4096
#define VSC9953_VLAN_CHECK(vid) \
(((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
+#define VSC9953_DEFAULT_AGE_TIME 300
#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
#define MIIMIND_OPR_PEND 0x00000004
+#define VSC9953_BITMASK(offset) ((BIT(offset)) - 1)
+#define VSC9953_ENC_BITFIELD(target, offset, width) \
+ (((target) & VSC9953_BITMASK(width)) << (offset))
+
+#define VSC9953_IO_ADDR(target, offset) ((target) + (offset << 2))
+
+#define VSC9953_IO_REG(target, offset) (VSC9953_IO_ADDR(target, offset))
+#define VSC9953_VCAP_CACHE_ENTRY_DAT(target, ri) \
+ VSC9953_IO_REG(target, (0x2 + (ri)))
+
+#define VSC9953_VCAP_CACHE_MASK_DAT(target, ri) \
+ VSC9953_IO_REG(target, (0x42 + (ri)))
+
+#define VSC9953_VCAP_CACHE_TG_DAT(target) VSC9953_IO_REG(target, 0xe2)
+#define VSC9953_VCAP_CFG_MV_CFG(target) VSC9953_IO_REG(target, 0x1)
+#define VSC9953_VCAP_CFG_MV_CFG_SIZE(target) \
+ VSC9953_ENC_BITFIELD(target, 0, 16)
+
+#define VSC9953_VCAP_CFG_UPDATE_CTRL(target) VSC9953_IO_REG(target, 0x0)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(target) \
+ VSC9953_ENC_BITFIELD(target, 22, 3)
+
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(target) \
+ VSC9953_ENC_BITFIELD(target, 3, 16)
+
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
+#define VSC9953_VCAP_CACHE_ACTION_DAT(target, ri) \
+ VSC9953_IO_REG(target, (0x82 + (ri)))
+
+#define VSC9953_VCAP_CACHE_CNT_DAT(target, ri) \
+ VSC9953_IO_REG(target, (0xc2 + (ri)))
+
+#define VSC9953_PORT_OFFSET 1
+#define VSC9953_IS1_CNT 256
+#define VSC9953_IS2_CNT 1024
+#define VSC9953_ES0_CNT 1024
+
+#define BITS_TO_DWORD(in) (1 + (((in) - 1) / 32))
+#define ENTRY_WORDS_ES0 BITS_TO_DWORD(29)
+#define ENTRY_WORDS_IS1 BITS_TO_DWORD(376)
+#define ENTRY_WORDS_IS2 BITS_TO_DWORD(376)
+#define ES0_ACT_WIDTH BITS_TO_DWORD(91)
+#define ES0_CNT_WIDTH BITS_TO_DWORD(1)
+#define IS1_ACT_WIDTH BITS_TO_DWORD(320)
+#define IS1_CNT_WIDTH BITS_TO_DWORD(4)
+#define IS2_ACT_WIDTH BITS_TO_DWORD(103 - 2 * VSC9953_PORT_OFFSET)
+#define IS2_CNT_WIDTH BITS_TO_DWORD(4 * 32)
+#define ES0_ACT_COUNT (VSC9953_ES0_CNT + VSC9953_MAX_PORTS)
+#define IS1_ACT_COUNT (VSC9953_IS1_CNT + 1)
+#define IS2_ACT_COUNT (VSC9953_IS2_CNT + VSC9953_MAX_PORTS + 2)
+
+/* TCAM entries */
+enum tcam_sel {
+ TCAM_SEL_ENTRY = BIT(0),
+ TCAM_SEL_ACTION = BIT(1),
+ TCAM_SEL_COUNTER = BIT(2),
+ TCAM_SEL_ALL = VSC9953_BITMASK(3),
+};
+
+enum tcam_cmd {
+ TCAM_CMD_WRITE = 0,
+ TCAM_CMD_READ = 1,
+ TCAM_CMD_MOVE_UP = 2,
+ TCAM_CMD_MOVE_DOWN = 3,
+ TCAM_CMD_INITIALIZE = 4,
+};
+
struct vsc9953_mdio_info {
struct vsc9953_mii_mng *regs;
char *name;
u32 port_mode[12];
};
+#define PGID_DST_START 0
+#define PGID_AGGR_START 64
+#define PGID_SRC_START 80
+
struct vsc9953_ana_pgid {
u32 port_grp_id[91];
};
struct vsc9953_ana_ana_tables ana_tables;
u32 reserved2[14];
struct vsc9953_ana_ana ana;
- u32 reserved3[22];
+ u32 reserved3[21];
struct vsc9953_ana_pgid port_id_tbl;
u32 reserved4[549];
struct vsc9953_ana_pfc pfc[10];
/* VSC9953 SYS structure */
+struct vsc9953_rx_cntrs {
+ u32 c_rx_oct;
+ u32 c_rx_uc;
+ u32 c_rx_mc;
+ u32 c_rx_bc;
+ u32 c_rx_short;
+ u32 c_rx_frag;
+ u32 c_rx_jabber;
+ u32 c_rx_crc;
+ u32 c_rx_symbol_err;
+ u32 c_rx_sz_64;
+ u32 c_rx_sz_65_127;
+ u32 c_rx_sz_128_255;
+ u32 c_rx_sz_256_511;
+ u32 c_rx_sz_512_1023;
+ u32 c_rx_sz_1024_1526;
+ u32 c_rx_sz_jumbo;
+ u32 c_rx_pause;
+ u32 c_rx_control;
+ u32 c_rx_long;
+ u32 c_rx_cat_drop;
+ u32 c_rx_red_prio_0;
+ u32 c_rx_red_prio_1;
+ u32 c_rx_red_prio_2;
+ u32 c_rx_red_prio_3;
+ u32 c_rx_red_prio_4;
+ u32 c_rx_red_prio_5;
+ u32 c_rx_red_prio_6;
+ u32 c_rx_red_prio_7;
+ u32 c_rx_yellow_prio_0;
+ u32 c_rx_yellow_prio_1;
+ u32 c_rx_yellow_prio_2;
+ u32 c_rx_yellow_prio_3;
+ u32 c_rx_yellow_prio_4;
+ u32 c_rx_yellow_prio_5;
+ u32 c_rx_yellow_prio_6;
+ u32 c_rx_yellow_prio_7;
+ u32 c_rx_green_prio_0;
+ u32 c_rx_green_prio_1;
+ u32 c_rx_green_prio_2;
+ u32 c_rx_green_prio_3;
+ u32 c_rx_green_prio_4;
+ u32 c_rx_green_prio_5;
+ u32 c_rx_green_prio_6;
+ u32 c_rx_green_prio_7;
+ u32 reserved[20];
+};
+
+struct vsc9953_tx_cntrs {
+ u32 c_tx_oct;
+ u32 c_tx_uc;
+ u32 c_tx_mc;
+ u32 c_tx_bc;
+ u32 c_tx_col;
+ u32 c_tx_drop;
+ u32 c_tx_pause;
+ u32 c_tx_sz_64;
+ u32 c_tx_sz_65_127;
+ u32 c_tx_sz_128_255;
+ u32 c_tx_sz_256_511;
+ u32 c_tx_sz_512_1023;
+ u32 c_tx_sz_1024_1526;
+ u32 c_tx_sz_jumbo;
+ u32 c_tx_yellow_prio_0;
+ u32 c_tx_yellow_prio_1;
+ u32 c_tx_yellow_prio_2;
+ u32 c_tx_yellow_prio_3;
+ u32 c_tx_yellow_prio_4;
+ u32 c_tx_yellow_prio_5;
+ u32 c_tx_yellow_prio_6;
+ u32 c_tx_yellow_prio_7;
+ u32 c_tx_green_prio_0;
+ u32 c_tx_green_prio_1;
+ u32 c_tx_green_prio_2;
+ u32 c_tx_green_prio_3;
+ u32 c_tx_green_prio_4;
+ u32 c_tx_green_prio_5;
+ u32 c_tx_green_prio_6;
+ u32 c_tx_green_prio_7;
+ u32 c_tx_aged;
+ u32 reserved[33];
+};
+
+struct vsc9953_drop_cntrs {
+ u32 c_dr_local;
+ u32 c_dr_tail;
+ u32 c_dr_yellow_prio_0;
+ u32 c_dr_yellow_prio_1;
+ u32 c_dr_yellow_prio_2;
+ u32 c_dr_yellow_prio_3;
+ u32 c_dr_yellow_prio_4;
+ u32 c_dr_yellow_prio_5;
+ u32 c_dr_yellow_prio_6;
+ u32 c_dr_yellow_prio_7;
+ u32 c_dr_green_prio_0;
+ u32 c_dr_green_prio_1;
+ u32 c_dr_green_prio_2;
+ u32 c_dr_green_prio_3;
+ u32 c_dr_green_prio_4;
+ u32 c_dr_green_prio_5;
+ u32 c_dr_green_prio_6;
+ u32 c_dr_green_prio_7;
+ u32 reserved[46];
+};
+
struct vsc9953_sys_stat {
- u32 rx_cntrs[64];
- u32 tx_cntrs[64];
- u32 drop_cntrs[64];
+ struct vsc9953_rx_cntrs rx_cntrs;
+ struct vsc9953_tx_cntrs tx_cntrs;
+ struct vsc9953_drop_cntrs drop_cntrs;
u32 reserved1[6];
};
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