mmc: fsl_esdhc: Fix SDR104 and HS200 support

[oweals/u-boot.git] / include / fsl_sec.h

diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index bffabc89b99d8e378462240466ec778e77075d13..c0d2c7e8667921727be914d2cb42f29eba37240e 100644 (file)
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Common internal memory map for some Freescale SoCs
  *
  * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __FSL_SEC_H
@@ -24,7 +23,7 @@
 #define sec_in16(a)       in_be16(a)
 #define sec_clrbits32     clrbits_be32
 #define sec_setbits32     setbits_be32
-#else
+#elif defined(CONFIG_SYS_FSL_HAS_SEC)
 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
 #endif
 
@@ -67,6 +66,9 @@ struct rng4tst {
        };
        u32 rsvd1[40];
 #define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
+#define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
+#define RNG_STATE_HANDLE_MASK  \
+       (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
        u32 rdsta;              /*RNG DRNG Status Register*/
        u32 rsvd2[15];
 };
@@ -91,8 +93,7 @@ typedef struct ccsr_sec {
        struct {
                u32     ms;     /* DECO LIODN Register, MS */
                u32     ls;     /* DECO LIODN Register, LS */
-       } decoliodnr[8];
-       u8      res4[0x40];
+       } decoliodnr[16];
        u32     dar;            /* DECO Avail Register */
        u32     drr;            /* DECO Reset Register */
        u8      res5[0x4d8];
@@ -119,10 +120,18 @@ typedef struct ccsr_sec {
        u32     chanum_ls;      /* CHA Number Register, LS */
        u32     secvid_ms;      /* SEC Version ID Register, MS */
        u32     secvid_ls;      /* SEC Version ID Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+       u8      res9[0x6f020];
+#else
        u8      res9[0x6020];
+#endif
        u32     qilcr_ms;       /* Queue Interface LIODN CFG Register, MS */
        u32     qilcr_ls;       /* Queue Interface LIODN CFG Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+       u8      res10[0x8ffd8];
+#else
        u8      res10[0x8fd8];
+#endif
 } ccsr_sec_t;
 
 #define SEC_CTPR_MS_AXI_LIODN          0x08000000
@@ -215,6 +224,8 @@ struct sg_entry {
 #define SG_ENTRY_OFFSET_SHIFT  0
 };
 
+#define BLOB_SIZE(x)           ((x) + 32 + 16) /* Blob buffer size */
+
 #if defined(CONFIG_MX6) || defined(CONFIG_MX7)
 /* Job Ring Base Address */
 #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
@@ -274,8 +285,6 @@ struct sg_entry {
 #define PERM                   0x0000B008      /* Clear on release, lock SMAP
                                                 * lock SMAG group 1 Blob */
 
-#define BLOB_SIZE(x)       (x + 32 + 16) /* Blob buffer size */
-
 /* HAB WRAPPED KEY header */
 #define WRP_HDR_SIZE           0x08
 #define HDR_TAG                        0x81
@@ -303,7 +312,7 @@ struct sg_entry {
  */
 int blob_dek(const u8 *src, u8 *dst, u8 len);
 
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
 int sec_init_idx(uint8_t);
 #endif
 int sec_init(void);