colibri_imx6: fix video stdout in default environment

[oweals/u-boot.git] / include / fsl_esdhc.h

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 02b362d5e36e2d74a06960d4005f39f67f32adf0..e148eaa880477f0fc73794ad5ee26cdb477f6d4c 100644 (file)
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -1,10 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * FSL SD/MMC Defines
  *-------------------------------------------------------------------
  *
  * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
- *
- * SPDX-License-Identifier:    GPL-2.0+
+ * Copyright 2020 NXP
  */
 
 #ifndef  __FSL_ESDHC_H__
@@ -25,22 +25,14 @@
 #define SYSCTL_INITA           0x08000000
 #define SYSCTL_TIMEOUT_MASK    0x000f0000
 #define SYSCTL_CLOCK_MASK      0x0000fff0
-#if !defined(CONFIG_FSL_USDHC)
 #define SYSCTL_CKEN            0x00000008
 #define SYSCTL_PEREN           0x00000004
 #define SYSCTL_HCKEN           0x00000002
 #define SYSCTL_IPGEN           0x00000001
-#endif
 #define SYSCTL_RSTA            0x01000000
 #define SYSCTL_RSTC            0x02000000
 #define SYSCTL_RSTD            0x04000000
 
-#define VENDORSPEC_CKEN                0x00004000
-#define VENDORSPEC_PEREN       0x00002000
-#define VENDORSPEC_HCKEN       0x00001000
-#define VENDORSPEC_IPGEN       0x00000800
-#define VENDORSPEC_INIT                0x20007809
-
 #define IRQSTAT                        0x0002e030
 #define IRQSTAT_DMAE           (0x10000000)
 #define IRQSTAT_AC12E          (0x01000000)
@@ -106,6 +98,8 @@
 #define PROCTL_INIT            0x00000020
 #define PROCTL_DTW_4           0x00000002
 #define PROCTL_DTW_8           0x00000004
+#define PROCTL_D3CD            0x00000008
+#define PROCTL_VOLT_SEL                0x00000400
 
 #define CMDARG                 0x0002e008
 
@@ -130,7 +124,7 @@
 #define XFERTYP_DMAEN          0x00000001
 
 #define CINS_TIMEOUT           1000
-#define PIO_TIMEOUT            100000
+#define PIO_TIMEOUT            500
 
 #define DSADDR         0x2e004
 
@@ -164,20 +158,18 @@
 #define BLKATTR_SIZE(x)        (x & 0x1fff)
 #define MAX_BLK_CNT    0x7fff  /* so malloc will have enough room with 32M */
 
-#define ESDHC_HOSTCAPBLT_VS18  0x04000000
-#define ESDHC_HOSTCAPBLT_VS30  0x02000000
-#define ESDHC_HOSTCAPBLT_VS33  0x01000000
-#define ESDHC_HOSTCAPBLT_SRS   0x00800000
-#define ESDHC_HOSTCAPBLT_DMAS  0x00400000
-#define ESDHC_HOSTCAPBLT_HSS   0x00200000
-
-#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
+/* Host controller capabilities register */
+#define HOSTCAPBLT_VS18                0x04000000
+#define HOSTCAPBLT_VS30                0x02000000
+#define HOSTCAPBLT_VS33                0x01000000
+#define HOSTCAPBLT_SRS         0x00800000
+#define HOSTCAPBLT_DMAS                0x00400000
+#define HOSTCAPBLT_HSS         0x00200000
 
 struct fsl_esdhc_cfg {
        phys_addr_t esdhc_base;
        u32     sdhc_clk;
        u8      max_bus_width;
-       int     wp_enable;
        int     vs18_enable; /* Use 1.8V if set to 1 */
        struct mmc_config cfg;
 };
@@ -215,6 +207,10 @@ struct fsl_esdhc_cfg {
 int fsl_esdhc_mmc_init(bd_t *bis);
 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
 void fdt_fixup_esdhc(void *blob, bd_t *bd);
+#ifdef MMC_SUPPORTS_TUNING
+static inline int fsl_esdhc_execute_tuning(struct udevice *dev,
+                                          uint32_t opcode) {return 0; }
+#endif
 #else
 static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
 static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}