mmc: fsl_esdhc: Fix SDR104 and HS200 support
[oweals/u-boot.git] / include / cpsw.h
index 9f8ce8850f51d1958596a76edf5f2c1c06fb3def..786f8b385b75da4f74c89f110e04fb6faa0f4e73 100644 (file)
 #ifndef _CPSW_H_
 #define _CPSW_H_
 
+#include <dm/ofnode.h>
+
+/* reg offset */
+#define CPSW_HOST_PORT_OFFSET  0x108
+#define CPSW_SLAVE0_OFFSET     0x208
+#define CPSW_SLAVE1_OFFSET     0x308
+#define CPSW_SLAVE_SIZE                0x100
+#define CPSW_CPDMA_OFFSET      0x800
+#define CPSW_HW_STATS          0x900
+#define CPSW_STATERAM_OFFSET   0xa00
+#define CPSW_CPTS_OFFSET       0xc00
+#define CPSW_ALE_OFFSET                0xd00
+#define CPSW_SLIVER0_OFFSET    0xd80
+#define CPSW_SLIVER1_OFFSET    0xdc0
+#define CPSW_BD_OFFSET         0x2000
+#define CPSW_MDIO_DIV          0xff
+
+#define AM335X_GMII_SEL_OFFSET 0x630
+
 struct cpsw_slave_data {
        u32             slave_reg_ofs;
        u32             sliver_reg_ofs;
        int             phy_addr;
        int             phy_if;
-       int             phy_of_handle;
+       ofnode          phy_of_handle;
+       int             max_speed;
 };
 
 enum {
@@ -50,10 +70,16 @@ struct cpsw_platform_data {
        u32     active_slave;
        bool    rmii_clock_external;
        u8      version;
+       const char *phy_sel_compat;
+       u32     syscon_addr;
+       const char *macid_sel_compat;
 };
 
 int cpsw_register(struct cpsw_platform_data *data);
-int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr);
+int ti_cm_get_macid_addr(struct udevice *dev, int slave,
+                        struct cpsw_platform_data *data);
+void ti_cm_get_macid(struct udevice *dev, struct cpsw_platform_data *data,
+                    u8 *mac_addr);
 int cpsw_get_slave_phy_addr(struct udevice *dev, int slave);
 
 #endif /* _CPSW_H_  */