Merge branch 'master' of git://git.denx.de/u-boot-sh

[oweals/u-boot.git] / include / configs / vme8349.h

diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index dd8aae511730a16df0166cfaaeca90540584b431..1c3430d849183161bb56252d066b50751b8d29aa 100644 (file)
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -25,8 +25,6 @@
 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2             /* support for 2nd PCI controller */
 
-#define CONFIG_SYS_IMMR                0xE0000000
-
 #undef CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START       0x00000000      /* memtest region */
 #define CONFIG_SYS_MEMTEST_END         0x00100000
@@ -53,9 +51,7 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE            0x00000000      /* DDR is sys memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000      /* DDR is sys memory*/
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING
@@ -70,15 +66,9 @@
 #define CONFIG_SYS_FLASH_BASE          0xf8000000      /* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE          128             /* flash size in MB */
 
-/* FLASH */
-#define CONFIG_SYS_BR0_PRELIM          (0xF8000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR0_PRELIM          (OR_AM_128MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_WINDOW1_BASE                0xf0000000
 
-/* WINDOW1 */
-#define CONFIG_SYS_BR1_PRELIM          (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM          (OR_AM_256KB | OR_GPCM_SETA)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device*/
@@ -106,15 +96,6 @@
 #define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB */
 #define CONFIG_SYS_MALLOC_LEN          (256 * 1024)    /* Malloc size */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  no DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #undef CONFIG_SYS_LB_SDRAM     /* if board has SDRAM on local bus */
 
 /*
@@ -269,12 +250,6 @@
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
-                                HID0_ENABLE_INSTRUCTION_CACHE)
-
-#define CONFIG_SYS_HID2                HID2_HBE
-
 #define CONFIG_SYS_GPIO1_PRELIM
 #define CONFIG_SYS_GPIO1_DIR   0x00100000
 #define CONFIG_SYS_GPIO1_DAT   0x00100000