sun50i: h5: Add initial NanoPi NEO2 support

[oweals/u-boot.git] / include / configs / o2dnt-common.h

diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index 183c4492848dd78787d29f6e30f9e2d4b35c4b81..1b4200bcbffc8fcd881454442aee18fee4b7e1f0 100644 (file)
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -40,7 +40,6 @@
  * Serial console configuration
  */
 #define CONFIG_PSC_CONSOLE     5       /* console is on PSC5 */
-#define CONFIG_BAUDRATE                115200  /* ... at 115200 bps */
 #define CONFIG_SYS_BAUDRATE_TABLE \
        { 9600, 19200, 38400, 57600, 115200, 230400 }
 
@@ -49,8 +48,6 @@
  * 0x40000000 - 0x4fffffff - PCI Memory
  * 0x50000000 - 0x50ffffff - PCI IO Space
  */
-#undef CONFIG_PCI
-#define CONFIG_PCI_PNP         1
 
 #define CONFIG_PCI_MEM_BUS     0x40000000
 #define CONFIG_PCI_MEM_PHYS    CONFIG_PCI_MEM_BUS
@@ -63,9 +60,6 @@
 #define CONFIG_SYS_XLB_PIPELINING      1
 
 /* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
 
 #define CONFIG_TIMESTAMP       /* Print image info with timestamp */
 
@@ -74,20 +68,9 @@
 /*
  * Supported commands
  */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
 #endif
-#ifdef CONFIG_POST
-#define CONFIG_CMD_DIAG
-#endif
 
 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
 /* Boot low with 16 or 32 MB Flash */
@@ -96,26 +79,13 @@
 #error "CONFIG_SYS_TEXT_BASE value is invalid"
 #endif
 
-/*
- * Autobooting
- * Be selective on what keys can delay or stop the autoboot process
- * To stop use: "++++++++++"
- */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
-                               "press password to stop\n", bootdelay
-#define CONFIG_AUTOBOOT_STOP_STR       "++++++++++"
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define DEBUG_BOOTKEYS         0
-
-#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT "run master"
 
 #undef CONFIG_BOOTARGS
 
-#if !defined(CONFIG_CONSOLE_DEV)
-#define CONFIG_CONSOLE_DEV     "ttyPSC1"
+#if !defined(CONSOLE_DEV)
+#define CONSOLE_DEV    "ttyPSC1"
 #endif
 
 /*
@@ -150,7 +120,7 @@
        "addmem=setenv bootargs ${bootargs} ${memlimit}\0"              \
        "addmisc=sete bootargs ${bootargs} ${miscargs}\0"               \
        "addtty=sete bootargs ${bootargs} console="                     \
-               CONFIG_CONSOLE_DEV ",${baudrate}\0"                     \
+               CONSOLE_DEV ",${baudrate}\0"                    \
        "bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
        "kernel_addr_r=600000\0"                                        \
        "initrd_high=0x03e00000\0"                                      \
@@ -201,27 +171,6 @@
 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2   /* define for 66MHz speed */
 #endif
 
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C                        1       /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE          1       /* Select I2C module #1 or #2 */
-#define CONFIG_SYS_I2C_SPEED           100000  /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE           0x7F
-
-/*
- * EEPROM configuration:
- *
- * O2DNT board is equiped with Ramtron FRAM device FM24CL16
- * 16 Kib Ferroelectric Nonvolatile serial RAM memory
- * organized as 2048 x 8 bits and addressable as eight I2C devices
- * 0x50 ... 0x57 each 256 bytes in size
- *
- */
-#define CONFIG_SYS_I2C_FRAM
-#define CONFIG_SYS_I2C_EEPROM_ADDR             0x50    /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      3
 /*
  * There is no write delay with FRAM, write operations are performed at bus
  * speed. Thus, no status polling or write delay is needed.
@@ -266,13 +215,13 @@
 #define CONFIG_SYS_INIT_RAM_ADDR       MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END                MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE       MPC5XXX_SRAM_POST_SIZE
 #else
 /* End of used area in DPRAM */
-#define CONFIG_SYS_INIT_RAM_END                MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE       MPC5XXX_SRAM_SIZE
 #endif
 
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - \
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - \
                                         GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
@@ -306,7 +255,6 @@
  */
 #define CONFIG_SYS_LONGHELP                    /* undef to save memory     */
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE              1024    /* Console I/O Buffer Size  */
@@ -345,9 +293,6 @@
 /*
  * DT support
  */
-#define CONFIG_OF_LIBFDT       1
-#define CONFIG_OF_BOARD_SETUP  1
-
 #define OF_CPU                 "PowerPC,5200@0"
 #define OF_SOC                 "soc5200@f0000000"
 #define OF_TBCLK               (bd->bi_busfreq / 4)