#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
+#define CONFIG_SCSI
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
/* SPI */
#ifdef CONFIG_FSL_DSPI
-#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#endif
/* MMC */
#define CONFIG_MMC
#ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_FSL_MEMAC
#define CONFIG_PHYLIB
#define CONFIG_PHYLIB_10G
-#define CONFIG_CMD_MII
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_TERANETICS
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
#define CONFIG_MII /* MII PHY management */
-#define CONFIG_ETHPRIME "DPNI1"
+#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
#include <asm/fsl_secure_boot.h>