Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

[oweals/u-boot.git] / include / configs / T104xRDB.h

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 56ddef07f5ea0a317dde932ec2f17a671d96e133..7cc3db943e509bd763518311b1f7c3bcae6f2511 100644 (file)
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -13,7 +13,7 @@
 
 #ifdef CONFIG_RAMBOOT_PBL
 
-#ifndef CONFIG_SECURE_BOOT
+#ifndef CONFIG_NXP_ESBC
 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
 #else
 #define CONFIG_SYS_FSL_PBL_PBI \
@@ -32,7 +32,7 @@
 #define BOOT_PAGE_OFFSET               0x27000
 
 #ifdef CONFIG_NAND
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_U_BOOT_HDR_SIZE         (16 << 10)
 /*
  * HDR would be appended at end of image and copied to DDR along
@@ -145,13 +145,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE1                   /* PCIE controller 1 */
 #define CONFIG_PCIE2                   /* PCIE controller 2 */
 #define CONFIG_PCIE3                   /* PCIE controller 3 */
 #define CONFIG_PCIE4                   /* PCIE controller 4 */
 
-#define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -165,7 +163,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 #define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_ENV_OFFSET              (512 * 0x800)
 #elif defined(CONFIG_NAND)
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_RAMBOOT_NAND
 #define CONFIG_BOOTSCRIPT_COPY_RAM
 #endif
@@ -524,51 +522,55 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
 #define        CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
-#define        CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 #define        CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
 #define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0x90000000
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc10000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 #endif
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
 #define CONFIG_SYS_PCIE3_MEM_VIRT      0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc20000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE      0x10000000      /* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
 #endif
 
 /* controller 4, Base address 203000 */
 #ifdef CONFIG_PCIE4
 #define CONFIG_SYS_PCIE4_MEM_VIRT      0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS      0xc30000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE      0x10000000      /* 256M */
 #define CONFIG_SYS_PCIE4_IO_VIRT       0xf8030000
-#define CONFIG_SYS_PCIE4_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS       0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE       0x00010000      /* 64k */
 #endif
 
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
 #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
 #endif /* CONFIG_PCI */