test/py: test_ut.py: Ensure we use bytes

[oweals/u-boot.git] / include / clk-uclass.h

diff --git a/include/clk-uclass.h b/include/clk-uclass.h
index 07c10654955cb7bdb75f4d2a923a4c1b5cdf3ff0..e76d98e2f6751611de309f7c2764d852c08e67d3 100644 (file)
--- a/include/clk-uclass.h
+++ b/include/clk-uclass.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (c) 2015 Google, Inc
  * Written by Simon Glass <sjg@chromium.org>
  * Copyright (c) 2016, NVIDIA CORPORATION.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _CLK_UCLASS_H
@@ -12,7 +11,8 @@
 /* See clk.h for background documentation. */
 
 #include <clk.h>
-#include <fdtdec.h>
+
+struct ofnode_phandle_args;
 
 /**
  * struct clk_ops - The functions that a clock driver must implement.
@@ -37,7 +37,7 @@ struct clk_ops {
         * @return 0 if OK, or a negative error code.
         */
        int (*of_xlate)(struct clk *clock,
-                       struct fdtdec_phandle_args *args);
+                       struct ofnode_phandle_args *args);
        /**
         * request - Request a translated clock.
         *
@@ -76,6 +76,14 @@ struct clk_ops {
         * @return new rate, or -ve error code.
         */
        ulong (*set_rate)(struct clk *clk, ulong rate);
+       /**
+        * set_parent() - Set current clock parent
+        *
+        * @clk:        The clock to manipulate.
+        * @parent:     New clock parent.
+        * @return zero on success, or -ve error code.
+        */
+       int (*set_parent)(struct clk *clk, struct clk *parent);
        /**
         * enable() - Enable a clock.
         *