mmc: fsl_esdhc: Fix SDR104 and HS200 support

[oweals/u-boot.git] / include / ahci.h

diff --git a/include/ahci.h b/include/ahci.h
index 90e850929b7d4c625dee3baeb7ed4307af2fe0cc..fb96dd886115c77ddb103d3942e4c3356c06accc 100644 (file)
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) Freescale Semiconductor, Inc. 2006.
  * Author: Jason Jin<Jason.jin@freescale.com>
  *         Zhang Wei<wei.zhang@freescale.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef _AHCI_H_
 #define _AHCI_H_
@@ -58,6 +57,10 @@
 #define PORT_SCR_ERR           0x30 /* SATA phy register: SError */
 #define PORT_SCR_ACT           0x34 /* SATA phy register: SActive */
 
+#ifdef CONFIG_SUNXI_AHCI
+#define PORT_P0DMACR           0x70 /* SUNXI specific "DMA register" */
+#endif
+
 /* PORT_IRQ_{STAT,MASK} bits */
 #define PORT_IRQ_COLD_PRES     (1 << 31) /* cold presence detect */
 #define PORT_IRQ_TF_ERR                (1 << 30) /* task file error */
@@ -131,23 +134,37 @@ struct ahci_sg {
 };
 
 struct ahci_ioports {
-       u32     cmd_addr;
-       u32     scr_addr;
-       u32     port_mmio;
+       void __iomem    *port_mmio;
        struct ahci_cmd_hdr     *cmd_slot;
        struct ahci_sg          *cmd_tbl_sg;
-       u32     cmd_tbl;
+       ulong   cmd_tbl;
        u32     rx_fis;
 };
 
-struct ahci_probe_ent {
+/**
+ * struct ahci_uc_priv - information about an AHCI controller
+ *
+ * When driver model is used, this is accessible using dev_get_uclass_priv(dev)
+ * where dev is the controller (although at present it sometimes stands alone).
+ */
+struct ahci_uc_priv {
+#if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
+       /*
+        * TODO(sjg@chromium.org): Drop this once this structure is only used
+        * in a driver-model context (i.e. attached to a device with
+        * dev_get_uclass_priv()
+        */
+       struct udevice *dev;
+#else
        pci_dev_t       dev;
+#endif
        struct ahci_ioports     port[AHCI_MAX_PORTS];
+       u16 *ataid[AHCI_MAX_PORTS];
        u32     n_ports;
        u32     hard_port_no;
        u32     host_flags;
        u32     host_set_flags;
-       u32     mmio_base;
+       void __iomem *mmio_base;
        u32     pio_mask;
        u32     udma_mask;
        u32     flags;
@@ -156,6 +173,116 @@ struct ahci_probe_ent {
        u32     link_port_map; /*linkup port map*/
 };
 
-int ahci_init(u32 base);
+struct ahci_ops {
+       /**
+        * reset() - reset the controller
+        *
+        * @dev:        Controller to reset
+        * @return 0 if OK, -ve on error
+        */
+       int (*reset)(struct udevice *dev);
+
+       /**
+        * port_status() - get the status of a SATA port
+        *
+        * @dev:        Controller to reset
+        * @port:       Port number to check (0 for first)
+        * @return 0 if detected, -ENXIO if nothing on port, other -ve on error
+        */
+       int (*port_status)(struct udevice *dev, int port);
+
+       /**
+        * scan() - scan SATA ports
+        *
+        * @dev:        Controller to scan
+        * @return 0 if OK, -ve on error
+        */
+       int (*scan)(struct udevice *dev);
+};
+
+#define ahci_get_ops(dev)        ((struct ahci_ops *)(dev)->driver->ops)
+
+/**
+ * sata_reset() - reset the controller
+ *
+ * @dev:       Controller to reset
+ * @return 0 if OK, -ve on error
+ */
+int sata_reset(struct udevice *dev);
+
+/**
+ * sata_port_status() - get the status of a SATA port
+ *
+ * @dev:       Controller to reset
+ * @port:      Port number to check (0 for first)
+ * @return 0 if detected, -ENXIO if nothin on port, other -ve on error
+ */
+int sata_dm_port_status(struct udevice *dev, int port);
+
+/**
+ * sata_scan() - scan SATA ports
+ *
+ * @dev:       Controller to scan
+ * @return 0 if OK, -ve on error
+ */
+int sata_scan(struct udevice *dev);
+
+int ahci_init(void __iomem *base);
+int ahci_reset(void __iomem *base);
+
+/**
+ * ahci_init_one_dm() - set up a single AHCI port
+ *
+ * @dev: Controller to init
+ */
+int ahci_init_one_dm(struct udevice *dev);
+
+/**
+ * ahci_start_ports_dm() - start all AHCI ports for a controller
+ *
+ * @dev: Controller containing ports to start
+ */
+int ahci_start_ports_dm(struct udevice *dev);
+
+/**
+ * ahci_init_dm() - init AHCI for a controller, finding all ports
+ *
+ * @dev: Device to init
+ */
+int ahci_init_dm(struct udevice *dev, void __iomem *base);
+
+/**
+ * ahci_bind_scsi() - bind a new SCSI bus as a child
+ *
+ * Note that the SCSI bus device will itself bind block devices
+ *
+ * @ahci_dev: AHCI parent device
+ * @devp: Returns new SCSI bus device
+ * @return 0 if OK, -ve on error
+ */
+int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp);
+
+/**
+ * ahci_probe_scsi() - probe and scan the attached SCSI bus
+ *
+ * Note that the SCSI device will itself bind block devices for any storage
+ * devices it finds.
+ *
+ * @ahci_dev: AHCI parent device
+ * @base: Base address of AHCI port
+ * @return 0 if OK, -ve on error
+ */
+int ahci_probe_scsi(struct udevice *ahci_dev, ulong base);
+
+/**
+ * ahci_probe_scsi_pci() - probe and scan the attached SCSI bus on PCI
+ *
+ * Note that the SCSI device will itself bind block devices for any storage
+ * devices it finds.
+ *
+ * @ahci_dev: AHCI parent device
+ * @return 0 if OK, -ve on error
+ */
+int ahci_probe_scsi_pci(struct udevice *ahci_dev);
 
 #endif