Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti

[oweals/u-boot.git] / drivers / ram / rockchip / sdram_rk3288.c

diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
index d99bf12476283827e0329ef3d4174cff455af54a..64d704ef267372a8e8add19d787b86f0ca266bd0 100644 (file)
--- a/drivers/ram/rockchip/sdram_rk3288.c
+++ b/drivers/ram/rockchip/sdram_rk3288.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 /*
  * (C) Copyright 2015 Google, Inc
  * Copyright 2014 Rockchip Inc.
  *
- * SPDX-License-Identifier:     GPL-2.0
- *
  * Adapted from coreboot.
  */
 
@@ -12,17 +11,21 @@
 #include <dm.h>
 #include <dt-structs.h>
 #include <errno.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
 #include <ram.h>
 #include <regmap.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
-#include <asm/arch/ddr_rk3288.h>
-#include <asm/arch/grf_rk3288.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/sdram_common.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru.h>
+#include <asm/arch-rockchip/ddr_rk3288.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/arch-rockchip/sdram_rk3288.h>
+#include <linux/delay.h>
 #include <linux/err.h>
 #include <power/regulator.h>
 #include <power/rk8xx_pmic.h>
@@ -37,7 +40,7 @@ struct dram_info {
        struct chan_info chan[2];
        struct ram_info info;
        struct clk ddr_clk;
-       struct rk3288_cru *cru;
+       struct rockchip_cru *cru;
        struct rk3288_grf *grf;
        struct rk3288_sgrf *sgrf;
        struct rk3288_pmu *pmu;
@@ -80,7 +83,8 @@ const int ddrconf_table[] = {
 #define DQS_GATE_TRAINING_ERROR_RANK0  (1 << 4)
 #define DQS_GATE_TRAINING_ERROR_RANK1  (2 << 4)
 
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+       (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
 {
        int i;
@@ -92,7 +96,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
        }
 }
 
-static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
+static void ddr_reset(struct rockchip_cru *cru, u32 ch, u32 ctl, u32 phy)
 {
        u32 phy_ctl_srstn_shift = 4 + 5 * ch;
        u32 ctl_psrstn_shift = 3 + 5 * ch;
@@ -109,7 +113,7 @@ static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
                     phy << phy_srstn_shift);
 }
 
-static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
+static void ddr_phy_ctl_reset(struct rockchip_cru *cru, u32 ch, u32 n)
 {
        u32 phy_ctl_srstn_shift = 4 + 5 * ch;
 
@@ -117,7 +121,7 @@ static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
                     1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
 }
 
-static void phy_pctrl_reset(struct rk3288_cru *cru,
+static void phy_pctrl_reset(struct rockchip_cru *cru,
                            struct rk3288_ddr_publ *publ,
                            int channel)
 {
@@ -1001,7 +1005,7 @@ static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
 
        priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron");
 #endif
-       ret = regmap_init_mem(dev, &params->map);
+       ret = regmap_init_mem(dev_ofnode(dev), &params->map);
        if (ret)
                return ret;
 #endif
@@ -1036,7 +1040,8 @@ static int conv_of_platdata(struct udevice *dev)
 
 static int rk3288_dmc_probe(struct udevice *dev)
 {
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+       (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
        struct rk3288_sdram_params *plat = dev_get_platdata(dev);
        struct udevice *dev_clk;
        struct regmap *map;
@@ -1045,7 +1050,8 @@ static int rk3288_dmc_probe(struct udevice *dev)
        struct dram_info *priv = dev_get_priv(dev);
 
        priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+       (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
        ret = conv_of_platdata(dev);
        if (ret)
@@ -1112,12 +1118,14 @@ U_BOOT_DRIVER(dmc_rk3288) = {
        .id = UCLASS_RAM,
        .of_match = rk3288_dmc_ids,
        .ops = &rk3288_dmc_ops,
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+       (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
        .ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata,
 #endif
        .probe = rk3288_dmc_probe,
        .priv_auto_alloc_size = sizeof(struct dram_info),
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+       (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
        .platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params),
 #endif
 };