+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mapmem.h>
+#include <dm/devres.h>
#include <linux/io.h>
#include <linux/err.h>
#include <dm.h>
const struct fdt_property *prop;
u32 *pin_data;
int npins, size, pin_size;
- int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
+ int mux_reg, conf_reg, input_reg;
+ u32 input_val, mux_mode, config_val;
u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
int i, j = 0;
dev_dbg(dev, "%s: %s\n", __func__, config->name);
- if (info->flags & SHARE_MUX_CONF_REG)
+ if (info->flags & IMX8_USE_SCU)
+ pin_size = SHARE_IMX8_PIN_SIZE;
+ else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = SHARE_FSL_PIN_SIZE;
else
pin_size = FSL_PIN_SIZE;
npins = size / pin_size;
- /*
- * Refer to linux documentation for details:
- * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
- */
- for (i = 0; i < npins; i++) {
- mux_reg = pin_data[j++];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
- mux_reg = -1;
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- conf_reg = mux_reg;
- } else {
- conf_reg = pin_data[j++];
- if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
- conf_reg = -1;
- }
+ if (info->flags & IMX8_USE_SCU) {
+ imx_pinctrl_scu_conf_pins(info, pin_data, npins);
+ } else {
+ /*
+ * Refer to linux documentation for details:
+ * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+ */
+ for (i = 0; i < npins; i++) {
+ mux_reg = pin_data[j++];
- if ((mux_reg == -1) || (conf_reg == -1)) {
- dev_err(dev, "Error mux_reg or conf_reg\n");
- devm_kfree(dev, pin_data);
- return -EINVAL;
- }
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
- input_reg = pin_data[j++];
- mux_mode = pin_data[j++];
- input_val = pin_data[j++];
- config_val = pin_data[j++];
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ conf_reg = mux_reg;
+ } else {
+ conf_reg = pin_data[j++];
+ if (!(info->flags & ZERO_OFFSET_VALID) &&
+ !conf_reg)
+ conf_reg = -1;
+ }
- dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, "
- "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
- mux_reg, conf_reg, input_reg, mux_mode, input_val,
- config_val);
+ if ((mux_reg == -1) || (conf_reg == -1)) {
+ dev_err(dev, "Error mux_reg or conf_reg\n");
+ devm_kfree(dev, pin_data);
+ return -EINVAL;
+ }
- if (config_val & IMX_PAD_SION)
- mux_mode |= IOMUXC_CONFIG_SION;
+ input_reg = pin_data[j++];
+ mux_mode = pin_data[j++];
+ input_val = pin_data[j++];
+ config_val = pin_data[j++];
- config_val &= ~IMX_PAD_SION;
+ dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, "
+ "input_reg 0x%x, mux_mode 0x%x, "
+ "input_val 0x%x, config_val 0x%x\n",
+ mux_reg, conf_reg, input_reg, mux_mode,
+ input_val, config_val);
- /* Set Mux */
- if (info->flags & SHARE_MUX_CONF_REG) {
- clrsetbits_le32(info->base + mux_reg, info->mux_mask,
- mux_mode << mux_shift);
- } else {
- writel(mux_mode, info->base + mux_reg);
- }
+ if (config_val & IMX_PAD_SION)
+ mux_mode |= IOMUXC_CONFIG_SION;
- dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg,
- mux_mode);
+ config_val &= ~IMX_PAD_SION;
- /*
- * Set select input
- *
- * If the select input value begins with 0xff, it's a quirky
- * select input and the value should be interpreted as below.
- * 31 23 15 7 0
- * | 0xff | shift | width | select |
- * It's used to work around the problem that the select
- * input for some pin is not implemented in the select
- * input register but in some general purpose register.
- * We encode the select input value, width and shift of
- * the bit field into input_val cell of pin function ID
- * in device tree, and then decode them here for setting
- * up the select input bits in general purpose register.
- */
+ /* Set Mux */
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ clrsetbits_le32(info->base + mux_reg,
+ info->mux_mask,
+ mux_mode << mux_shift);
+ } else {
+ writel(mux_mode, info->base + mux_reg);
+ }
+
+ dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
+ mux_reg, mux_mode);
- if (input_val >> 24 == 0xff) {
- u32 val = input_val;
- u8 select = val & 0xff;
- u8 width = (val >> 8) & 0xff;
- u8 shift = (val >> 16) & 0xff;
- u32 mask = ((1 << width) - 1) << shift;
- /*
- * The input_reg[i] here is actually some IOMUXC general
- * purpose register, not regular select input register.
- */
- val = readl(info->base + input_reg);
- val &= ~mask;
- val |= select << shift;
- writel(val, info->base + input_reg);
- } else if (input_reg) {
/*
- * Regular select input register can never be at offset
- * 0, and we only print register value for regular case.
+ * Set select input
+ *
+ * If the select input value begins with 0xff,
+ * it's a quirky select input and the value should
+ * be interpreted as below.
+ * 31 23 15 7 0
+ * | 0xff | shift | width | select |
+ * It's used to work around the problem that the
+ * select input for some pin is not implemented in
+ * the select input register but in some general
+ * purpose register. We encode the select input
+ * value, width and shift of the bit field into
+ * input_val cell of pin function ID in device tree,
+ * and then decode them here for setting up the select
+ * input bits in general purpose register.
*/
- if (info->input_sel_base)
- writel(input_val, info->input_sel_base +
- input_reg);
- else
- writel(input_val, info->base + input_reg);
-
- dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n",
- input_reg, input_val);
- }
- /* Set config */
- if (!(config_val & IMX_NO_PAD_CTL)) {
- if (info->flags & SHARE_MUX_CONF_REG) {
- clrsetbits_le32(info->base + conf_reg,
- ~info->mux_mask, config_val);
- } else {
- writel(config_val, info->base + conf_reg);
+ if (input_val >> 24 == 0xff) {
+ u32 val = input_val;
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some
+ * IOMUXC general purpose register, not
+ * regular select input register.
+ */
+ val = readl(info->base + input_reg);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, info->base + input_reg);
+ } else if (input_reg) {
+ /*
+ * Regular select input register can never be
+ * at offset 0, and we only print register
+ * value for regular case.
+ */
+ if (info->input_sel_base)
+ writel(input_val,
+ info->input_sel_base +
+ input_reg);
+ else
+ writel(input_val,
+ info->base + input_reg);
+
+ dev_dbg(dev, "select_input: offset 0x%x val "
+ "0x%x\n", input_reg, input_val);
}
- dev_dbg(dev, "write config: offset 0x%x val 0x%x\n",
- conf_reg, config_val);
+ /* Set config */
+ if (!(config_val & IMX_NO_PAD_CTL)) {
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ clrsetbits_le32(info->base + conf_reg,
+ ~info->mux_mask,
+ config_val);
+ } else {
+ writel(config_val,
+ info->base + conf_reg);
+ }
+
+ dev_dbg(dev, "write config: offset 0x%x val "
+ "0x%x\n", conf_reg, config_val);
+ }
}
}
priv->dev = dev;
priv->info = info;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
- &size);
+ if (info->flags & IMX8_USE_SCU)
+ return 0;
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct imx_pinctrl_priv *priv = dev_get_priv(dev);
struct imx_pinctrl_soc_info *info = priv->info;
+ if (info->flags & IMX8_USE_SCU)
+ return 0;
+
if (info->input_sel_base)
unmap_sysmem(info->input_sel_base);
if (info->base)
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