common: Move ARM cache operations out of common.h

[oweals/u-boot.git] / drivers / net / pic32_eth.c

diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c
index 385aad5b7e1d735afdcecdcc5bec4570a6c73efa..3458440b6ff7ff59924cc7a0d36b6f6063131d1a 100644 (file)
--- a/drivers/net/pic32_eth.c
+++ b/drivers/net/pic32_eth.c
@@ -1,17 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
  *
- * SPDX-License-Identifier:    GPL-2.0+
- *
  */
 #include <common.h>
+#include <cpu_func.h>
 #include <errno.h>
 #include <dm.h>
 #include <net.h>
 #include <miiphy.h>
 #include <console.h>
+#include <time.h>
 #include <wait_bit.h>
 #include <asm/gpio.h>
+#include <linux/mii.h>
 
 #include "pic32_eth.h"
 
@@ -64,8 +66,8 @@ static int pic32_mii_init(struct pic32eth_dev *priv)
        writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 
        /* wait till busy */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         CONFIG_SYS_HZ, false);
 
        /* turn controller ON to access PHY over MII */
        writel(ETHCON_ON, &ectl_p->con1.set);
@@ -239,8 +241,8 @@ static void pic32_ctrl_reset(struct pic32eth_dev *priv)
        writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 
        /* wait till busy */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         CONFIG_SYS_HZ, false);
        /* decrement received buffcnt to zero. */
        while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
                writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
@@ -375,8 +377,8 @@ static void pic32_eth_stop(struct udevice *dev)
        mdelay(10);
 
        /* wait until everything is down */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    2 * CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         2 * CONFIG_SYS_HZ, false);
 
        /* clear any existing interrupt event */
        writel(0xffffffff, &ectl_p->irq.clr);
@@ -561,8 +563,7 @@ static int pic32_eth_probe(struct udevice *dev)
                phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 
        /* phy reset gpio */
-       gpio_request_by_name_nodev(gd->fdt_blob, dev_of_offset(dev),
-                                  "reset-gpios", 0,
+       gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
                                   &priv->rst_gpio, GPIOD_IS_OUT);
 
        priv->phyif     = pdata->phy_interface;