+// SPDX-License-Identifier: GPL-2.0
/*
* Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
*
*
* Rami Rosen <rosenr@marvell.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
+#include <cpu_func.h>
#include <dm.h>
+#include <log.h>
#include <net.h>
#include <netdev.h>
#include <config.h>
#include <malloc.h>
+#include <asm/cache.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
#include <linux/errno.h>
#include <phy.h>
#include <miiphy.h>
#include <asm/arch/soc.h>
#include <linux/compat.h>
#include <linux/mbus.h>
+#include <asm-generic/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
# error Marvell mvneta requires PHYLIB
#endif
-/* Some linux -> U-Boot compatibility stuff */
-#define netdev_err(dev, fmt, args...) \
- printf(fmt, ##args)
-#define netdev_warn(dev, fmt, args...) \
- printf(fmt, ##args)
-#define netdev_info(dev, fmt, args...) \
- printf(fmt, ##args)
-
#define CONFIG_NR_CPUS 1
#define ETH_HLEN 14 /* Total octets in header */
#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
+#define MVNETA_WIN_SIZE_MASK (0xffff0000)
#define MVNETA_BASE_ADDR_ENABLE 0x2290
+#define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
+#define MVNETA_PORT_ACCESS_PROTECT 0x2294
+#define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
#define MVNETA_PORT_CONFIG 0x2400
#define MVNETA_UNI_PROMISC_MODE BIT(0)
#define MVNETA_DEF_RXQ(q) ((q) << 1)
#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
+#define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
+#define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
#define MVNETA_GMAC_AN_SPEED_EN BIT(7)
+#define MVNETA_GMAC_SET_FC_EN BIT(8)
+#define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
+#define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
#define MVNETA_MIB_COUNTERS_BASE 0x3080
#define MVNETA_MIB_LATE_COLLISION 0x7c
#define MVNETA_DA_FILT_SPEC_MCAST 0x3400
int init;
int phyaddr;
struct phy_device *phydev;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct gpio_desc phy_reset_gpio;
+#endif
struct mii_dev *bus;
};
*/
#define BD_SPACE (1 << 20)
+/*
+ * Dummy implementation that can be overwritten by a board
+ * specific function
+ */
+__weak int board_network_enable(struct mii_dev *bus)
+{
+ return 0;
+}
+
/* Utility/helper methods */
/* Write helper method */
u32 val;
/* Only 255 descriptors can be added at once ; Assume caller
- * process TX desriptors in quanta less than 256
+ * process TX descriptors in quanta less than 256
*/
val = pend_desc;
mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
}
+static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
+{
+ /* phy_addr is set to invalid value for fixed link */
+ return pp->phyaddr > PHY_MAX_ADDR;
+}
+
+
/* Start the Ethernet port RX and TX activity */
static void mvneta_port_up(struct mvneta_port *pp)
{
/* Assign port SDMA configuration */
mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
- /* Enable PHY polling in hardware for U-Boot */
- val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
- val |= MVNETA_PHY_POLLING_ENABLE;
- mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
+ /* Enable PHY polling in hardware if not in fixed-link mode */
+ if (!mvneta_port_is_fixed_link(pp)) {
+ val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
+ val |= MVNETA_PHY_POLLING_ENABLE;
+ mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
+ }
mvneta_set_ucast_table(pp, -1);
mvneta_set_special_mcast_table(pp, -1);
mvneta_set_ucast_addr(pp, addr[5], queue);
}
+static int mvneta_write_hwaddr(struct udevice *dev)
+{
+ mvneta_mac_addr_set(dev_get_priv(dev),
+ ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
+ rxq_def);
+
+ return 0;
+}
+
/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
u32 phys_addr, u32 cookie)
if (rxq->descs == NULL)
return -ENOMEM;
+ WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
+
rxq->last_desc = rxq->size - 1;
/* Set Rx descriptors queue starting address */
if (txq->descs == NULL)
return -ENOMEM;
+ WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
+
txq->last_desc = txq->size - 1;
/* Set maximum bandwidth for enabled TXQs */
struct phy_device *phydev = pp->phydev;
int status_change = 0;
+ if (mvneta_port_is_fixed_link(pp)) {
+ debug("Using fixed link, skip link adjust\n");
+ return;
+ }
+
if (phydev->link) {
if ((pp->speed != phydev->speed) ||
(pp->duplex != phydev->duplex)) {
}
/* platform glue : initialize decoding windows */
+
+/*
+ * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
+ * First layer is: GbE Address window that resides inside the GBE unit,
+ * Second layer is: Fabric address window which is located in the NIC400
+ * (South Fabric).
+ * To simplify the address decode configuration for Armada3700, we bypass the
+ * first layer of GBE decode window by setting the first window to 4GB.
+ */
+static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
+{
+ /*
+ * Set window size to 4GB, to bypass GBE address decode, leave the
+ * work to MBUS decode window
+ */
+ mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
+
+ /* Enable GBE address decode window 0 by set bit 0 to 0 */
+ clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
+ MVNETA_BASE_ADDR_ENABLE_BIT);
+
+ /* Set GBE address decode window 0 to full Access (read or write) */
+ setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
+ MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
+}
+
static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
{
const struct mbus_dram_target_info *dram;
mvneta_port_power_up(pp, pp->phy_interface);
if (!pp->init || pp->link == 0) {
- /* Set phy address of the port */
- mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
- phydev = phy_connect(pp->bus, pp->phyaddr, dev,
- pp->phy_interface);
-
- pp->phydev = phydev;
- phy_config(phydev);
- phy_startup(phydev);
- if (!phydev->link) {
- printf("%s: No link.\n", phydev->dev->name);
- return -1;
- }
+ if (mvneta_port_is_fixed_link(pp)) {
+ u32 val;
- /* Full init on first call */
- mvneta_init(dev);
- pp->init = 1;
- } else {
- /* Upon all following calls, this is enough */
- mvneta_port_up(pp);
- mvneta_port_enable(pp);
+ pp->init = 1;
+ pp->link = 1;
+ mvneta_init(dev);
+
+ val = MVNETA_GMAC_FORCE_LINK_UP |
+ MVNETA_GMAC_IB_BYPASS_AN_EN |
+ MVNETA_GMAC_SET_FC_EN |
+ MVNETA_GMAC_ADVERT_FC_EN |
+ MVNETA_GMAC_SAMPLE_TX_CFG_EN;
+
+ if (pp->duplex)
+ val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
+
+ if (pp->speed == SPEED_1000)
+ val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
+ else if (pp->speed == SPEED_100)
+ val |= MVNETA_GMAC_CONFIG_MII_SPEED;
+
+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
+ } else {
+ /* Set phy address of the port */
+ mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
+
+ phydev = phy_connect(pp->bus, pp->phyaddr, dev,
+ pp->phy_interface);
+ if (!phydev) {
+ printf("phy_connect failed\n");
+ return -ENODEV;
+ }
+
+ pp->phydev = phydev;
+ phy_config(phydev);
+ phy_startup(phydev);
+ if (!phydev->link) {
+ printf("%s: No link.\n", phydev->dev->name);
+ return -1;
+ }
+
+ /* Full init on first call */
+ mvneta_init(dev);
+ pp->init = 1;
+ return 0;
+ }
}
+ /* Upon all following calls, this is enough */
+ mvneta_port_up(pp);
+ mvneta_port_enable(pp);
+
return 0;
}
*/
*packetp = data;
- mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
+ /*
+ * Only mark one descriptor as free
+ * since only one was processed
+ */
+ mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
}
return rx_bytes;
struct eth_pdata *pdata = dev_get_platdata(dev);
struct mvneta_port *pp = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct mii_dev *bus;
unsigned long addr;
void *bd_space;
+ int ret;
+ int fl_node;
/*
* Allocate buffer area for descs and rx_buffers. This is only
* done once for all interfaces. As only one interface can
- * be active. Make this area DMA save by disabling the D-cache
+ * be active. Make this area DMA safe by disabling the D-cache
*/
if (!buffer_loc.tx_descs) {
+ u32 size;
+
/* Align buffer area for descs and rx_buffers to 1MiB */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
+ flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE);
mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
DCACHE_OFF);
buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
+ size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
+ ARCH_DMA_MINALIGN);
+ memset(buffer_loc.tx_descs, 0, size);
buffer_loc.rx_descs = (struct mvneta_rx_desc *)
- ((phys_addr_t)bd_space +
- MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
- buffer_loc.rx_buffers = (phys_addr_t)
- (bd_space +
- MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
- MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
+ ((phys_addr_t)bd_space + size);
+ size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
+ ARCH_DMA_MINALIGN);
+ buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
}
pp->base = (void __iomem *)pdata->iobase;
/* Configure MBUS address windows */
- mvneta_conf_mbus_windows(pp);
+ if (device_is_compatible(dev, "marvell,armada-3700-neta"))
+ mvneta_bypass_mbus_windows(pp);
+ else
+ mvneta_conf_mbus_windows(pp);
/* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
pp->phy_interface = pdata->phy_interface;
- /* Now read phyaddr from DT */
- addr = fdtdec_get_int(blob, node, "phy", 0);
- addr = fdt_node_offset_by_phandle(blob, addr);
- pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
+ /* fetch 'fixed-link' property from 'neta' node */
+ fl_node = fdt_subnode_offset(blob, node, "fixed-link");
+ if (fl_node != -FDT_ERR_NOTFOUND) {
+ /* set phy_addr to invalid value for fixed link */
+ pp->phyaddr = PHY_MAX_ADDR + 1;
+ pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
+ pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
+ } else {
+ /* Now read phyaddr from DT */
+ addr = fdtdec_get_int(blob, node, "phy", 0);
+ addr = fdt_node_offset_by_phandle(blob, addr);
+ pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
+ }
bus = mdio_alloc();
if (!bus) {
bus->priv = (void *)pp;
pp->bus = bus;
- return mdio_register(bus);
+ ret = mdio_register(bus);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ gpio_request_by_name(dev, "phy-reset-gpios", 0,
+ &pp->phy_reset_gpio, GPIOD_IS_OUT);
+
+ if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
+ dm_gpio_set_value(&pp->phy_reset_gpio, 1);
+ mdelay(10);
+ dm_gpio_set_value(&pp->phy_reset_gpio, 0);
+ }
+#endif
+
+ return board_network_enable(bus);
}
static void mvneta_stop(struct udevice *dev)
.send = mvneta_send,
.recv = mvneta_recv,
.stop = mvneta_stop,
+ .write_hwaddr = mvneta_write_hwaddr,
};
static int mvneta_ofdata_to_platdata(struct udevice *dev)
struct eth_pdata *pdata = dev_get_platdata(dev);
const char *phy_mode;
- pdata->iobase = dev_get_addr(dev);
+ pdata->iobase = devfdt_get_addr(dev);
/* Get phy-mode / phy_interface from DT */
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
static const struct udevice_id mvneta_ids[] = {
{ .compatible = "marvell,armada-370-neta" },
{ .compatible = "marvell,armada-xp-neta" },
+ { .compatible = "marvell,armada-3700-neta" },
{ }
};
projects / oweals / u-boot.git / blobdiff