u8 deviceid;
u8 bank;
u8 no_1p8;
- bool pwrseq;
};
#if defined(CONFIG_ARCH_ZYNQMP)
[MMC_HS_200] = MMC_HS200_BUS_SPEED,
};
-#define SDHCI_HOST_CTRL2 0x3E
-#define SDHCI_CTRL2_MODE_MASK 0x7
-#define SDHCI_18V_SIGNAL 0x8
-#define SDHCI_CTRL_EXEC_TUNING 0x0040
-#define SDHCI_CTRL_TUNED_CLK 0x80
#define SDHCI_TUNING_LOOP_COUNT 40
static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
host = priv->host;
deviceid = priv->deviceid;
- ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl |= SDHCI_CTRL_EXEC_TUNING;
- sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
mdelay(1);
sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
mmc_send_cmd(mmc, &cmd, NULL);
- ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
udelay(1);
if (tuning_loop_counter < 0) {
ctrl &= ~SDHCI_CTRL_TUNED_CLK;
- sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
+ sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
}
if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
return;
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
- reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
- reg |= SDHCI_18V_SIGNAL;
- sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ reg |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
}
if (mmc->selected_mode > SD_HS &&
- mmc->selected_mode <= UHS_DDR50) {
- reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
- reg &= ~SDHCI_CTRL2_MODE_MASK;
- switch (mmc->selected_mode) {
- case UHS_SDR12:
- reg |= UHS_SDR12_BUS_SPEED;
- break;
- case UHS_SDR25:
- reg |= UHS_SDR25_BUS_SPEED;
- break;
- case UHS_SDR50:
- reg |= UHS_SDR50_BUS_SPEED;
- break;
- case UHS_SDR104:
- reg |= UHS_SDR104_BUS_SPEED;
- break;
- case UHS_DDR50:
- reg |= UHS_DDR50_BUS_SPEED;
- break;
- default:
- break;
- }
- sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
- }
+ mmc->selected_mode <= UHS_DDR50)
+ sdhci_set_uhs_timing(host);
}
#endif
host->max_clk = clock;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
+
ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
- host->mmc = &plat->mmc;
if (ret)
return ret;
- host->mmc->priv = host;
- host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);