*/
#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
#include <errno.h>
+#include <log.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>
-
-#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
-void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
-#else
-void *aligned_buffer;
-#endif
+#include <dm.h>
+#include <asm/cache.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <phys2bus.h>
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
}
}
-static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
- unsigned int start_addr)
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
+ u16 len, bool end)
+{
+ struct sdhci_adma_desc *desc;
+ u8 attr;
+
+ desc = &host->adma_desc_table[host->desc_slot];
+
+ attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
+ if (!end)
+ host->desc_slot++;
+ else
+ attr |= ADMA_DESC_ATTR_END;
+
+ desc->attr = attr;
+ desc->len = len;
+ desc->reserved = 0;
+ desc->addr_lo = lower_32_bits(dma_addr);
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ desc->addr_hi = upper_32_bits(dma_addr);
+#endif
+}
+
+static void sdhci_prepare_adma_table(struct sdhci_host *host,
+ struct mmc_data *data)
+{
+ uint trans_bytes = data->blocksize * data->blocks;
+ uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
+ int i = desc_count;
+ dma_addr_t dma_addr = host->start_addr;
+
+ host->desc_slot = 0;
+
+ while (--i) {
+ sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
+ dma_addr += ADMA_MAX_LEN;
+ trans_bytes -= ADMA_MAX_LEN;
+ }
+
+ sdhci_adma_desc(host, dma_addr, trans_bytes, true);
+
+ flush_cache((dma_addr_t)host->adma_desc_table,
+ ROUND(desc_count * sizeof(struct sdhci_adma_desc),
+ ARCH_DMA_MINALIGN));
+}
+#elif defined(CONFIG_MMC_SDHCI_SDMA)
+static void sdhci_prepare_adma_table(struct sdhci_host *host,
+ struct mmc_data *data)
+{}
+#endif
+#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
+static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
+ int *is_aligned, int trans_bytes)
{
- unsigned int stat, rdy, mask, timeout, block = 0;
- bool transfer_done = false;
-#ifdef CONFIG_MMC_SDHCI_SDMA
unsigned char ctrl;
+ void *buf;
+
+ if (data->flags == MMC_DATA_READ)
+ buf = data->dest;
+ else
+ buf = (void *)data->src;
+
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
+ if (host->flags & USE_ADMA64)
+ ctrl |= SDHCI_CTRL_ADMA64;
+ else if (host->flags & USE_ADMA)
+ ctrl |= SDHCI_CTRL_ADMA32;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+ if (host->flags & USE_SDMA &&
+ (host->force_align_buffer ||
+ (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
+ ((unsigned long)buf & 0x7) != 0x0))) {
+ *is_aligned = 0;
+ if (data->flags != MMC_DATA_READ)
+ memcpy(host->align_buffer, buf, trans_bytes);
+ buf = host->align_buffer;
+ }
+
+ host->start_addr = dma_map_single(buf, trans_bytes,
+ mmc_get_dma_dir(data));
+
+ if (host->flags & USE_SDMA) {
+ sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
+ SDHCI_DMA_ADDRESS);
+ } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
+ sdhci_prepare_adma_table(host, data);
+
+ sdhci_writel(host, lower_32_bits(host->adma_addr),
+ SDHCI_ADMA_ADDRESS);
+ if (host->flags & USE_ADMA64)
+ sdhci_writel(host, upper_32_bits(host->adma_addr),
+ SDHCI_ADMA_ADDRESS_HI);
+ }
+}
+#else
+static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
+ int *is_aligned, int trans_bytes)
+{}
#endif
+static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
+{
+ dma_addr_t start_addr = host->start_addr;
+ unsigned int stat, rdy, mask, timeout, block = 0;
+ bool transfer_done = false;
timeout = 1000000;
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
continue;
}
}
-#ifdef CONFIG_MMC_SDHCI_SDMA
- if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
+ if ((host->flags & USE_DMA) && !transfer_done &&
+ (stat & SDHCI_INT_DMA_END)) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
- start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
- start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
- sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
+ if (host->flags & USE_SDMA) {
+ start_addr &=
+ ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
+ start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
+ sdhci_writel(host, phys_to_bus((ulong)start_addr),
+ SDHCI_DMA_ADDRESS);
+ }
}
-#endif
if (timeout-- > 0)
udelay(10);
else {
return -ETIMEDOUT;
}
} while (!(stat & SDHCI_INT_DATA_END));
+
+ dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
+ mmc_get_dma_dir(data));
+
return 0;
}
int ret = 0;
int trans_bytes = 0, is_aligned = 1;
u32 mask, flags, mode;
- unsigned int time = 0, start_addr = 0;
+ unsigned int time = 0;
int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
ulong start = get_timer(0);
+ host->start_addr = 0;
/* Timeout unit - ms */
static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
/* We shouldn't wait for data inihibit for stop commands, even
though they might use busy signaling */
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
mask &= ~SDHCI_DATA_INHIBIT;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_INT_RESPONSE;
- if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
mask = SDHCI_INT_DATA_AVAIL;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags |= SDHCI_CMD_CRC;
if (cmd->resp_type & MMC_RSP_OPCODE)
flags |= SDHCI_CMD_INDEX;
- if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
flags |= SDHCI_CMD_DATA;
/* Set Transfer mode regarding to data flag */
if (data->flags == MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
-#ifdef CONFIG_MMC_SDHCI_SDMA
- if (data->flags == MMC_DATA_READ)
- start_addr = (unsigned long)data->dest;
- else
- start_addr = (unsigned long)data->src;
- if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
- (start_addr & 0x7) != 0x0) {
- is_aligned = 0;
- start_addr = (unsigned long)aligned_buffer;
- if (data->flags != MMC_DATA_READ)
- memcpy(aligned_buffer, data->src, trans_bytes);
+ if (host->flags & USE_DMA) {
+ mode |= SDHCI_TRNS_DMA;
+ sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
}
-#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
- /*
- * Always use this bounce-buffer when
- * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
- */
- is_aligned = 0;
- start_addr = (unsigned long)aligned_buffer;
- if (data->flags != MMC_DATA_READ)
- memcpy(aligned_buffer, data->src, trans_bytes);
-#endif
-
- sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
- mode |= SDHCI_TRNS_DMA;
-#endif
sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
data->blocksize),
SDHCI_BLOCK_SIZE);
}
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
-#ifdef CONFIG_MMC_SDHCI_SDMA
- if (data) {
- trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
- flush_cache(start_addr, trans_bytes);
- }
-#endif
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
start = get_timer(0);
do {
ret = -1;
if (!ret && data)
- ret = sdhci_transfer_data(host, data, start_addr);
+ ret = sdhci_transfer_data(host, data);
if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
udelay(1000);
if (!ret) {
if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
!is_aligned && (data->flags == MMC_DATA_READ))
- memcpy(data->dest, aligned_buffer, trans_bytes);
+ memcpy(data->dest, host->align_buffer, trans_bytes);
return 0;
}
return 0;
}
#endif
-static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
+int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
struct sdhci_host *host = mmc->priv;
unsigned int div, clk = 0, timeout;
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}
+void sdhci_set_uhs_timing(struct sdhci_host *host)
+{
+ struct mmc *mmc = host->mmc;
+ u32 reg;
+
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ reg &= ~SDHCI_CTRL_UHS_MASK;
+
+ switch (mmc->selected_mode) {
+ case UHS_SDR50:
+ case MMC_HS_52:
+ reg |= SDHCI_CTRL_UHS_SDR50;
+ break;
+ case UHS_DDR50:
+ case MMC_DDR_52:
+ reg |= SDHCI_CTRL_UHS_DDR50;
+ break;
+ case UHS_SDR104:
+ case MMC_HS_200:
+ reg |= SDHCI_CTRL_UHS_SDR104;
+ break;
+ default:
+ reg |= SDHCI_CTRL_UHS_SDR12;
+ }
+
+ sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+}
+
#ifdef CONFIG_DM_MMC
static int sdhci_set_ios(struct udevice *dev)
{
/* If available, call the driver specific "post" set_ios() function */
if (host->ops && host->ops->set_ios_post)
- host->ops->set_ios_post(host);
+ return host->ops->set_ios_post(host);
return 0;
}
static int sdhci_init(struct mmc *mmc)
{
struct sdhci_host *host = mmc->priv;
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
+ struct udevice *dev = mmc->dev;
+
+ gpio_request_by_name(dev, "cd-gpios", 0,
+ &host->cd_gpio, GPIOD_IS_IN);
+#endif
sdhci_reset(host, SDHCI_RESET_ALL);
- if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
- aligned_buffer = memalign(8, 512*1024);
- if (!aligned_buffer) {
+#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
+ host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
+ /*
+ * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
+ * is defined.
+ */
+ host->force_align_buffer = true;
+#else
+ if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
+ host->align_buffer = memalign(8, 512 * 1024);
+ if (!host->align_buffer) {
printf("%s: Aligned buffer alloc failed!!!\n",
__func__);
return -ENOMEM;
}
}
+#endif
sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
return sdhci_init(mmc);
}
+static int sdhci_deferred_probe(struct udevice *dev)
+{
+ int err;
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct sdhci_host *host = mmc->priv;
+
+ if (host->ops && host->ops->deferred_probe) {
+ err = host->ops->deferred_probe(host);
+ if (err)
+ return err;
+ }
+ return 0;
+}
+
+static int sdhci_get_cd(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct sdhci_host *host = mmc->priv;
+ int value;
+
+ /* If nonremovable, assume that the card is always present. */
+ if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
+ return 1;
+ /* If polling, assume that the card is always present. */
+ if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
+ return 1;
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ value = dm_gpio_get_value(&host->cd_gpio);
+ if (value >= 0) {
+ if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
+ return !value;
+ else
+ return value;
+ }
+#endif
+ value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
+ SDHCI_CARD_PRESENT);
+ if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
+ return !value;
+ else
+ return value;
+}
+
const struct dm_mmc_ops sdhci_ops = {
.send_cmd = sdhci_send_command,
.set_ios = sdhci_set_ios,
+ .get_cd = sdhci_get_cd,
+ .deferred_probe = sdhci_deferred_probe,
#ifdef MMC_SUPPORTS_TUNING
.execute_tuning = sdhci_execute_tuning,
#endif
u32 f_max, u32 f_min)
{
u32 caps, caps_1 = 0;
-
+#if CONFIG_IS_ENABLED(DM_MMC)
+ u64 dt_caps, dt_caps_mask;
+
+ dt_caps_mask = dev_read_u64_default(host->mmc->dev,
+ "sdhci-caps-mask", 0);
+ dt_caps = dev_read_u64_default(host->mmc->dev,
+ "sdhci-caps", 0);
+ caps = ~(u32)dt_caps_mask &
+ sdhci_readl(host, SDHCI_CAPABILITIES);
+ caps |= (u32)dt_caps;
+#else
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+#endif
+ debug("%s, caps: 0x%x\n", __func__, caps);
#ifdef CONFIG_MMC_SDHCI_SDMA
- if (!(caps & SDHCI_CAN_DO_SDMA)) {
+ if ((caps & SDHCI_CAN_DO_SDMA)) {
+ host->flags |= USE_SDMA;
+ } else {
+ debug("%s: Your controller doesn't support SDMA!!\n",
+ __func__);
+ }
+#endif
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+ if (!(caps & SDHCI_CAN_DO_ADMA2)) {
printf("%s: Your controller doesn't support SDMA!!\n",
__func__);
return -EINVAL;
}
+ host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
+
+ host->adma_addr = (dma_addr_t)host->adma_desc_table;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ host->flags |= USE_ADMA64;
+#else
+ host->flags |= USE_ADMA;
+#endif
#endif
if (host->quirks & SDHCI_QUIRK_REG32_RW)
host->version =
/* Check whether the clock multiplier is supported or not */
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
+#if CONFIG_IS_ENABLED(DM_MMC)
+ caps_1 = ~(u32)(dt_caps_mask >> 32) &
+ sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ caps_1 |= (u32)(dt_caps >> 32);
+#else
caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+#endif
+ debug("%s, caps_1: 0x%x\n", __func__, caps_1);
host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
SDHCI_CLOCK_MUL_SHIFT;
}
cfg->host_caps &= ~MMC_MODE_HS_52MHz;
}
- if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
- caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
-
- if (!(cfg->voltages & MMC_VDD_165_195) ||
- (host->quirks & SDHCI_QUIRK_NO_1_8_V))
+ if (!(cfg->voltages & MMC_VDD_165_195))
caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50);
projects / oweals / u-boot.git / blobdiff