Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / drivers / fpga / socfpga_arria10.c

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5fb9d6a1911a1148ef5a634759ae5a8ca2d45783..dfd3cbb461028e8d77a228f31db9a2dac7949970 100644 (file)
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -2,6 +2,8 @@
 /*
  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  */
+#include <image.h>
+#include <log.h>
 #include <asm/io.h>
 #include <asm/arch/fpga_manager.h>
 #include <asm/arch/reset_manager.h>
@@ -16,6 +18,8 @@
 #include <fs_loader.h>
 #include <wait_bit.h>
 #include <watchdog.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
 
 #define CFGWDTH_32     1
 #define MIN_BITSTREAM_SIZECHECK        230
@@ -30,9 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
 static const struct socfpga_fpga_manager *fpga_manager_base =
                (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
 
-static const struct socfpga_system_manager *system_manager_base =
-               (void *)SOCFPGA_SYSMGR_ADDRESS;
-
 static void fpgamgr_set_cd_ratio(unsigned long ratio);
 
 static uint32_t fpgamgr_get_msel(void)
@@ -818,7 +819,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
        }
 
        /* Disable all signals from HPS peripheral controller to FPGA */
-       writel(0, &system_manager_base->fpgaintf_en_global);
+       writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 
        /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
        socfpga_bridges_reset();
@@ -910,7 +911,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
        memset(&rbfinfo, 0, sizeof(rbfinfo));
 
        /* Disable all signals from hps peripheral controller to fpga */
-       writel(0, &system_manager_base->fpgaintf_en_global);
+       writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 
        /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
        socfpga_bridges_reset();