colibri_imx6: fix video stdout in default environment

[oweals/u-boot.git] / drivers / firmware / ti_sci.h

diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 1b601ff01bbe4ad200517ab58b2f14f26bfbf73a..327bb820f3a7f5ba5828b566b4a4434464f74a53 100644 (file)
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -15,6 +15,7 @@
 #define __TI_SCI_H
 
 /* Generic Messages */
+#include <linux/bitops.h>
 #define TI_SCI_MSG_ENABLE_WDT          0x0000
 #define TI_SCI_MSG_WAKE_RESET          0x0001
 #define TI_SCI_MSG_VERSION             0x0002
@@ -50,6 +51,7 @@
 #define TISCI_MSG_SET_PROC_BOOT_CTRL   0xc101
 #define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE        0xc120
 #define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
+#define TISCI_MSG_WAIT_PROC_BOOT_STATUS        0xc401
 
 /* Resource Management Requests */
 #define TI_SCI_MSG_GET_RESOURCE_RANGE  0x1500
@@ -57,7 +59,6 @@
 /* NAVSS resource management */
 /* Ringacc requests */
 #define TI_SCI_MSG_RM_RING_CFG                 0x1110
-#define TI_SCI_MSG_RM_RING_GET_CFG             0x1111
 
 /* PSI-L requests */
 #define TI_SCI_MSG_RM_PSIL_PAIR                        0x1280
@@ -71,13 +72,9 @@
 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG       0x1221
 
 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG           0x1205
-#define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG       0x1206
 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG           0x1215
-#define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG       0x1216
 #define TISCI_MSG_RM_UDMAP_FLOW_CFG            0x1230
 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG        0x1231
-#define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG                0x1232
-#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG    0x1233
 
 #define TISCI_MSG_FWL_SET              0x9000
 #define TISCI_MSG_FWL_GET              0x9001
@@ -708,7 +705,6 @@ struct ti_sci_msg_req_set_proc_boot_ctrl {
 /**
  * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image
  * @hdr:               Generic Header
- * @processor_id:      ID of processor
  * @cert_addr_low:     Lower 32bit (Little Endian) of certificate
  * @cert_addr_high:    Higher 32bit (Little Endian) of certificate
  *
@@ -717,11 +713,17 @@ struct ti_sci_msg_req_set_proc_boot_ctrl {
  */
 struct ti_sci_msg_req_proc_auth_boot_image {
        struct ti_sci_msg_hdr hdr;
-       u8 processor_id;
        u32 cert_addr_low;
        u32 cert_addr_high;
 } __packed;
 
+struct ti_sci_msg_resp_proc_auth_boot_image {
+       struct ti_sci_msg_hdr hdr;
+       u32 image_addr_low;
+       u32 image_addr_high;
+       u32 image_size;
+} __packed;
+
 /**
  * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status
  * @hdr:               Generic Header
@@ -767,6 +769,55 @@ struct ti_sci_msg_resp_get_proc_boot_status {
        u32 status_flags;
 } __packed;
 
+/**
+ * struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor
+ *                                              boot status
+ * @hdr:                       Generic Header
+ * @processor_id:              ID of processor
+ * @num_wait_iterations:       Total number of iterations we will check before
+ *                             we will timeout and give up
+ * @num_match_iterations:      How many iterations should we have continued
+ *                             status to account for status bits glitching.
+ *                             This is to make sure that match occurs for
+ *                             consecutive checks. This implies that the
+ *                             worst case should consider that the stable
+ *                             time should at the worst be num_wait_iterations
+ *                             num_match_iterations to prevent timeout.
+ * @delay_per_iteration_us:    Specifies how long to wait (in micro seconds)
+ *                             between each status checks. This is the minimum
+ *                             duration, and overhead of register reads and
+ *                             checks are on top of this and can vary based on
+ *                             varied conditions.
+ * @delay_before_iterations_us:        Specifies how long to wait (in micro seconds)
+ *                             before the very first check in the first
+ *                             iteration of status check loop. This is the
+ *                             minimum duration, and overhead of register
+ *                             reads and checks are.
+ * @status_flags_1_set_all_wait:If non-zero, Specifies that all bits of the
+ *                             status matching this field requested MUST be 1.
+ * @status_flags_1_set_any_wait:If non-zero, Specifies that at least one of the
+ *                             bits matching this field requested MUST be 1.
+ * @status_flags_1_clr_all_wait:If non-zero, Specifies that all bits of the
+ *                             status matching this field requested MUST be 0.
+ * @status_flags_1_clr_any_wait:If non-zero, Specifies that at least one of the
+ *                             bits matching this field requested MUST be 0.
+ *
+ * Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate
+ * message, or NACK in case of inability to satisfy request.
+ */
+struct ti_sci_msg_req_wait_proc_boot_status {
+       struct ti_sci_msg_hdr hdr;
+       u8 processor_id;
+       u8 num_wait_iterations;
+       u8 num_match_iterations;
+       u8 delay_per_iteration_us;
+       u8 delay_before_iterations_us;
+       u32 status_flags_1_set_all_wait;
+       u32 status_flags_1_set_any_wait;
+       u32 status_flags_1_clr_all_wait;
+       u32 status_flags_1_clr_any_wait;
+} __packed;
+
 /**
  * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
  *