common: Drop linux/delay.h from common header

[oweals/u-boot.git] / drivers / clk / rockchip / clk_rk322x.c

diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index 48ed14b2aff85342e0d1a1ba0a7f24e52fd0156e..912e1f6e92e751a8ec38c88a4f98ac8213a304fe 100644 (file)
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -7,6 +7,8 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
+#include <log.h>
+#include <malloc.h>
 #include <syscon.h>
 #include <asm/io.h>
 #include <asm/arch-rockchip/clock.h>
@@ -14,7 +16,9 @@
 #include <asm/arch-rockchip/hardware.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3228-cru.h>
+#include <linux/delay.h>
 #include <linux/log2.h>
+#include <linux/stringify.h>
 
 enum {
        VCO_MAX_HZ      = 3200U * 1000000,
@@ -121,10 +125,10 @@ static void rkclk_init(struct rk322x_cru *cru)
        assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 
        pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
-       assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
+       assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
 
        hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
-       assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
+       assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
 
        rk_clrsetreg(&cru->cru_clksel_con[0],
                     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
@@ -217,6 +221,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
        switch (periph) {
        case HCLK_EMMC:
        case SCLK_EMMC:
+       case SCLK_EMMC_SAMPLE:
                con = readl(&cru->cru_clksel_con[11]);
                mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
                con = readl(&cru->cru_clksel_con[12]);
@@ -293,6 +298,7 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
        switch (periph) {
        case HCLK_EMMC:
        case SCLK_EMMC:
+       case SCLK_EMMC_SAMPLE:
                rk_clrsetreg(&cru->cru_clksel_con[11],
                             EMMC_PLL_MASK,
                             mux << EMMC_PLL_SHIFT);
@@ -506,7 +512,7 @@ static int rk322x_clk_bind(struct udevice *dev)
                sys_child->priv = priv;
        }
 
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
        ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
        ret = rockchip_reset_bind(dev, ret, 9);
        if (ret)