common: Drop linux/delay.h from common header

[oweals/u-boot.git] / drivers / clk / rockchip / clk_rk3188.c

diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index d36cf8f3f27631c5b03766f1d20722f9cd48dd5e..11e3bd33cbeadadeb4de22079b191814a0c74df0 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * (C) Copyright 2015 Google, Inc
  * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #include <common.h>
@@ -10,20 +9,23 @@
 #include <dm.h>
 #include <dt-structs.h>
 #include <errno.h>
+#include <log.h>
+#include <malloc.h>
 #include <mapmem.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3188.h>
-#include <asm/arch/grf_rk3188.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3188.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <dt-bindings/clock/rk3188-cru.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/uclass-internal.h>
+#include <linux/delay.h>
+#include <linux/err.h>
 #include <linux/log2.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <linux/stringify.h>
 
 enum rk3188_clk_type {
        RK3188_CRU,
@@ -71,9 +73,6 @@ enum {
        SOCSTS_GPLL_LOCK        = 1 << 8,
 };
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-       ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)   ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _nr, _no) {\
@@ -126,7 +125,7 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
                               unsigned int hz, bool has_bwadj)
 {
        static const struct pll_div dpll_cfg[] = {
-               {.nf = 25, .nr = 2, .no = 1},
+               {.nf = 75, .nr = 1, .no = 6},
                {.nf = 400, .nr = 9, .no = 2},
                {.nf = 500, .nr = 9, .no = 2},
                {.nf = 100, .nr = 3, .no = 1},
@@ -269,14 +268,17 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
 
        switch (periph) {
        case HCLK_EMMC:
+       case SCLK_EMMC:
                con = readl(&cru->cru_clksel_con[12]);
                div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
                break;
        case HCLK_SDMMC:
+       case SCLK_SDMMC:
                con = readl(&cru->cru_clksel_con[11]);
                div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
                break;
        case HCLK_SDIO:
+       case SCLK_SDIO:
                con = readl(&cru->cru_clksel_con[12]);
                div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
                break;
@@ -284,7 +286,7 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
                return -EINVAL;
        }
 
-       return DIV_TO_RATE(gclk_rate, div);
+       return DIV_TO_RATE(gclk_rate, div) / 2;
 }
 
 static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
@@ -293,21 +295,25 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
        int src_clk_div;
 
        debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
-       src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+       /* mmc clock defaulg div 2 internal, need provide double in cru */
+       src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
        assert(src_clk_div <= 0x3f);
 
        switch (periph) {
        case HCLK_EMMC:
+       case SCLK_EMMC:
                rk_clrsetreg(&cru->cru_clksel_con[12],
                             EMMC_DIV_MASK << EMMC_DIV_SHIFT,
                             src_clk_div << EMMC_DIV_SHIFT);
                break;
        case HCLK_SDMMC:
+       case SCLK_SDMMC:
                rk_clrsetreg(&cru->cru_clksel_con[11],
                             MMC0_DIV_MASK << MMC0_DIV_SHIFT,
                             src_clk_div << MMC0_DIV_SHIFT);
                break;
        case HCLK_SDIO:
+       case SCLK_SDIO:
                rk_clrsetreg(&cru->cru_clksel_con[12],
                             SDIO_DIV_MASK << SDIO_DIV_SHIFT,
                             src_clk_div << SDIO_DIV_SHIFT);
@@ -344,8 +350,9 @@ static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
 static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
                                  int periph, uint freq)
 {
-       int src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+       int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
 
+       assert(src_clk_div < 128);
        switch (periph) {
        case SCLK_SPI0:
                assert(src_clk_div <= SPI0_DIV_MASK);
@@ -394,8 +401,8 @@ static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
         * reparent aclk_cpu_pre from apll to gpll
         * set up dependent divisors for PCLK/HCLK and ACLK clocks.
         */
-       aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ);
-       assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+       aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
+       assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 
        rk_clrsetreg(&cru->cru_clksel_con[0],
                     CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
@@ -466,6 +473,9 @@ static ulong rk3188_clk_get_rate(struct clk *clk)
        case HCLK_EMMC:
        case HCLK_SDMMC:
        case HCLK_SDIO:
+       case SCLK_EMMC:
+       case SCLK_SDMMC:
+       case SCLK_SDIO:
                new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
                                                clk->id);
                break;
@@ -505,6 +515,9 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
        case HCLK_EMMC:
        case HCLK_SDMMC:
        case HCLK_SDIO:
+       case SCLK_EMMC:
+       case SCLK_SDMMC:
+       case SCLK_SDIO:
                new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
                                                clk->id, rate);
                break;
@@ -530,7 +543,7 @@ static int rk3188_clk_ofdata_to_platdata(struct udevice *dev)
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
        struct rk3188_clk_priv *priv = dev_get_priv(dev);
 
-       priv->cru = (struct rk3188_cru *)dev_get_addr(dev);
+       priv->cru = dev_read_addr_ptr(dev);
 #endif
 
        return 0;
@@ -554,6 +567,9 @@ static int rk3188_clk_probe(struct udevice *dev)
 #endif
 
        rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
+
+       /* Init CPU frequency */
+       rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj);
 #endif
 
        return 0;
@@ -562,11 +578,29 @@ static int rk3188_clk_probe(struct udevice *dev)
 static int rk3188_clk_bind(struct udevice *dev)
 {
        int ret;
+       struct udevice *sys_child;
+       struct sysreset_reg *priv;
 
        /* The reset driver does not have a device node, so bind it here */
-       ret = device_bind_driver(gd->dm_root, "rk3188_sysreset", "reset", &dev);
+       ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+                                &sys_child);
+       if (ret) {
+               debug("Warning: No sysreset driver: ret=%d\n", ret);
+       } else {
+               priv = malloc(sizeof(struct sysreset_reg));
+               priv->glb_srst_fst_value = offsetof(struct rk3188_cru,
+                                                   cru_glb_srst_fst_value);
+               priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
+                                                   cru_glb_srst_snd_value);
+               sys_child->priv = priv;
+       }
+
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+       ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
+       ret = rockchip_reset_bind(dev, ret, 9);
        if (ret)
-               debug("Warning: No rk3188 reset driver: ret=%d\n", ret);
+               debug("Warning: software reset driver bind faile\n");
+#endif
 
        return 0;
 }