Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xx

[oweals/u-boot.git] / cpu / ppc4xx / start.S

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 072a6d1e9249cf5f8da755e91194b545db8c00bf..a96083caa581cc10b357ac52d6c8a5aeab46c5b3 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -2,6 +2,7 @@
  *  Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  *  Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
+ *  Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -699,7 +700,9 @@ _start:
 #endif /* CONFIG_IOP480 */
 
 /*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+    defined(CONFIG_405)
        /*----------------------------------------------------------------------- */
        /* Clear and set up some registers. */
        /*----------------------------------------------------------------------- */
@@ -727,13 +730,13 @@ _start:
        /*----------------------------------------------------------------------- */
        /* Enable two 128MB cachable regions. */
        /*----------------------------------------------------------------------- */
-       addis   r4,r0,0x8000
-       addi    r4,r4,0x0001
+       lis     r4,0x8000
+       ori     r4,r4,0x0001
        mticcr  r4                      /* instruction cache */
        isync
 
-       addis   r4,r0,0x0000
-       addi    r4,r4,0x0000
+       lis     r4,0x0000
+       ori     r4,r4,0x0000
        mtdccr  r4                      /* data cache */
 
 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
@@ -755,6 +758,35 @@ _start:
 #endif /* CONFIG_405EP */
 
 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
+#if defined(CONFIG_405EZ)
+       /********************************************************************
+        * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
+        *******************************************************************/
+       /*
+        * We can map the OCM on the PLB3, so map it at
+        * CFG_OCM_DATA_ADDR + 0x8000
+        */
+       lis     r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
+       ori     r3,r3,CFG_OCM_DATA_ADDR@l
+       ori     r3,r3,0x8270    /* 32K Offset, 16K for Bank 1, R/W/Enable */
+       mtdcr   ocmplb3cr1,r3           /* Set PLB Access */
+       ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
+       mtdcr   ocmplb3cr2,r3           /* Set PLB Access */
+       isync
+
+       lis     r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
+       ori     r3,r3,CFG_OCM_DATA_ADDR@l
+       ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
+       mtdcr   ocmdscr1, r3            /* Set Data Side */
+       mtdcr   ocmiscr1, r3            /* Set Instruction Side */
+       ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
+       mtdcr   ocmdscr2, r3            /* Set Data Side */
+       mtdcr   ocmiscr2, r3            /* Set Instruction Side */
+       addis   r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
+       mtdcr   ocmdsisdpc,r4
+
+       isync
+#else /* CONFIG_405EZ */
        /********************************************************************
         * Setup OCM - On Chip Memory
         *******************************************************************/
@@ -762,18 +794,20 @@ _start:
        lis     r0, 0x7FFF
        ori     r0, r0, 0xFFFF
        mfdcr   r3, ocmiscntl           /* get instr-side IRAM config */
-       mfdcr   r4, ocmdscntl   /* get data-side IRAM config */
-       and     r3, r3, r0      /* disable data-side IRAM */
-       and     r4, r4, r0      /* disable data-side IRAM */
-       mtdcr   ocmiscntl, r3   /* set instr-side IRAM config */
-       mtdcr   ocmdscntl, r4   /* set data-side IRAM config */
+       mfdcr   r4, ocmdscntl           /* get data-side IRAM config */
+       and     r3, r3, r0              /* disable data-side IRAM */
+       and     r4, r4, r0              /* disable data-side IRAM */
+       mtdcr   ocmiscntl, r3           /* set instr-side IRAM config */
+       mtdcr   ocmdscntl, r4           /* set data-side IRAM config */
        isync
 
-       addis   r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
+       lis     r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
+       ori     r3,r3,CFG_OCM_DATA_ADDR@l
        mtdcr   ocmdsarc, r3
        addis   r4, 0, 0xC000           /* OCM data area enabled */
        mtdcr   ocmdscntl, r4
        isync
+#endif /* CONFIG_405EZ */
 #endif
 
        /*----------------------------------------------------------------------- */