rename CFG_ macros to CONFIG_SYS

[oweals/u-boot.git] / cpu / arm920t / at91rm9200 / lowlevel_init.S

diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 6941d42dff03cc84bad5236f7944b9a11dcf41e1..66b07da08b668f4ba33e05f49dc3d02013b9efb6 100644 (file)
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -46,7 +46,7 @@
 #define MC_ASR         0xFFFFFF04
 #define MC_AASR                0xFFFFFF08
 #define EBI_CFGR       0xFFFFFF64
-#define SMC2_CSR       0xFFFFFF70
+#define SMC_CSR0       0xFFFFFF70
 
 /* clocks */
 #define PLLAR          0xFFFFFC28
@@ -79,7 +79,7 @@ lowlevel_init:
        /* Get the CKGR Base Address */
        ldr     r1, =AT91C_BASE_CKGR
        /* Main oscillator Enable register */
-#ifdef CFG_USE_MAIN_OSCILLATOR
+#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
        ldr     r0, =0x0000FF01         /* Enable main oscillator,  OSCOUNT = 0xFF */
 #else
        ldr     r0, =0x0000FF00         /* Disable main oscillator, OSCOUNT = 0xFF */
@@ -123,9 +123,9 @@ LoopOsc:
        cmp     r2, r0
        bne     2b
 
-       /* switch from FastBus to Synchronous clock mode */
+       /* switch from FastBus to Asynchronous clock mode */
        mrc     p15, 0, r0, c1, c0, 0
-       orr     r0, r0, #0x40000000     @ set bit 30 (nF) notFastBus
+       orr     r0, r0, #0xC0000000     @ set bit 31 (iA) and 30 (nF)
        mcr     p15, 0, r0, c1, c0, 0
 
        /* everything is fine now */
@@ -146,8 +146,8 @@ SMRDATA:
        .word MC_AASR_VAL
        .word EBI_CFGR
        .word EBI_CFGR_VAL
-       .word SMC2_CSR
-       .word SMC2_CSR_VAL
+       .word SMC_CSR0
+       .word SMC_CSR0_VAL
        .word PLLAR
        .word PLLAR_VAL
        .word PLLBR