MIPS: add compile time definition of L2 cache size
[oweals/u-boot.git] / configs / M54418TWR_serial_rmii_defconfig
index ee4dacd38c37bcb485bd6640da7d137cac7b3364..fd561f3d25eb5563ad469f05e1331980edf7c181 100644 (file)
@@ -6,8 +6,9 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2  ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMDLINE_EDITING is not set
+# CONFIG_AUTO_COMPLETE is not set
 CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
@@ -18,6 +19,13 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_rmii"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=1
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_MII=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CF_SPI=y