arm: zynq: Remove low level UART setting

[oweals/u-boot.git] / board / xilinx / zynq / zynq-zybo / ps7_init_gpl.c

diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index c41283704caaba7fa0f5f3e6a24eb1911026a4d7..fda6d18dd92ce6ccf02ed3e119883e84ad5d3656 100644 (file)
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -3647,64 +3647,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
        /* .. FINISH: LOCK IT BACK */
        /* .. START: SRAM/NOR SET OPMODE */
        /* .. FINISH: SRAM/NOR SET OPMODE */
-       /* .. START: UART REGISTERS */
-       /* .. BDIV = 0x6 */
-       /* .. ==> 0XE0001034[7:0] = 0x00000006U */
-       /* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-       /* .. CD = 0x7c */
-       /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-       /* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-       /* .. STPBRK = 0x0 */
-       /* .. ==> 0XE0001000[8:8] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-       /* .. STTBRK = 0x0 */
-       /* .. ==> 0XE0001000[7:7] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-       /* .. RSTTO = 0x0 */
-       /* .. ==> 0XE0001000[6:6] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-       /* .. TXDIS = 0x0 */
-       /* .. ==> 0XE0001000[5:5] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-       /* .. TXEN = 0x1 */
-       /* .. ==> 0XE0001000[4:4] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-       /* .. RXDIS = 0x0 */
-       /* .. ==> 0XE0001000[3:3] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-       /* .. RXEN = 0x1 */
-       /* .. ==> 0XE0001000[2:2] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-       /* .. TXRES = 0x1 */
-       /* .. ==> 0XE0001000[1:1] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-       /* .. RXRES = 0x1 */
-       /* .. ==> 0XE0001000[0:0] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-       /* .. CHMODE = 0x0 */
-       /* .. ==> 0XE0001004[9:8] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-       /* .. NBSTOP = 0x0 */
-       /* .. ==> 0XE0001004[7:6] = 0x00000000U */
-       /* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-       /* .. PAR = 0x4 */
-       /* .. ==> 0XE0001004[5:3] = 0x00000004U */
-       /* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-       /* .. CHRL = 0x0 */
-       /* .. ==> 0XE0001004[2:1] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-       /* .. CLKS = 0x0 */
-       /* .. ==> 0XE0001004[0:0] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
-       /* .. FINISH: UART REGISTERS */
        /* .. START: QSPI REGISTERS */
        /* .. Holdb_dr = 1 */
        /* .. ==> 0XE000D000[19:19] = 0x00000001U */
@@ -7944,70 +7886,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
        /* .. FINISH: LOCK IT BACK */
        /* .. START: SRAM/NOR SET OPMODE */
        /* .. FINISH: SRAM/NOR SET OPMODE */
-       /* .. START: UART REGISTERS */
-       /* .. BDIV = 0x6 */
-       /* .. ==> 0XE0001034[7:0] = 0x00000006U */
-       /* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-       /* .. CD = 0x7c */
-       /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-       /* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-       /* .. STPBRK = 0x0 */
-       /* .. ==> 0XE0001000[8:8] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-       /* .. STTBRK = 0x0 */
-       /* .. ==> 0XE0001000[7:7] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-       /* .. RSTTO = 0x0 */
-       /* .. ==> 0XE0001000[6:6] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-       /* .. TXDIS = 0x0 */
-       /* .. ==> 0XE0001000[5:5] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-       /* .. TXEN = 0x1 */
-       /* .. ==> 0XE0001000[4:4] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-       /* .. RXDIS = 0x0 */
-       /* .. ==> 0XE0001000[3:3] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-       /* .. RXEN = 0x1 */
-       /* .. ==> 0XE0001000[2:2] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-       /* .. TXRES = 0x1 */
-       /* .. ==> 0XE0001000[1:1] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-       /* .. RXRES = 0x1 */
-       /* .. ==> 0XE0001000[0:0] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-       /* .. IRMODE = 0x0 */
-       /* .. ==> 0XE0001004[11:11] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-       /* .. UCLKEN = 0x0 */
-       /* .. ==> 0XE0001004[10:10] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-       /* .. CHMODE = 0x0 */
-       /* .. ==> 0XE0001004[9:8] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-       /* .. NBSTOP = 0x0 */
-       /* .. ==> 0XE0001004[7:6] = 0x00000000U */
-       /* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-       /* .. PAR = 0x4 */
-       /* .. ==> 0XE0001004[5:3] = 0x00000004U */
-       /* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-       /* .. CHRL = 0x0 */
-       /* .. ==> 0XE0001004[2:1] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-       /* .. CLKS = 0x0 */
-       /* .. ==> 0XE0001004[0:0] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
-       /* .. FINISH: UART REGISTERS */
        /* .. START: QSPI REGISTERS */
        /* .. Holdb_dr = 1 */
        /* .. ==> 0XE000D000[19:19] = 0x00000001U */
@@ -12172,70 +12050,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
        /* .. FINISH: LOCK IT BACK */
        /* .. START: SRAM/NOR SET OPMODE */
        /* .. FINISH: SRAM/NOR SET OPMODE */
-       /* .. START: UART REGISTERS */
-       /* .. BDIV = 0x6 */
-       /* .. ==> 0XE0001034[7:0] = 0x00000006U */
-       /* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-       /* .. CD = 0x7c */
-       /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-       /* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-       /* .. STPBRK = 0x0 */
-       /* .. ==> 0XE0001000[8:8] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-       /* .. STTBRK = 0x0 */
-       /* .. ==> 0XE0001000[7:7] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-       /* .. RSTTO = 0x0 */
-       /* .. ==> 0XE0001000[6:6] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-       /* .. TXDIS = 0x0 */
-       /* .. ==> 0XE0001000[5:5] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-       /* .. TXEN = 0x1 */
-       /* .. ==> 0XE0001000[4:4] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-       /* .. RXDIS = 0x0 */
-       /* .. ==> 0XE0001000[3:3] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-       /* .. RXEN = 0x1 */
-       /* .. ==> 0XE0001000[2:2] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-       /* .. TXRES = 0x1 */
-       /* .. ==> 0XE0001000[1:1] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-       /* .. RXRES = 0x1 */
-       /* .. ==> 0XE0001000[0:0] = 0x00000001U */
-       /* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-       /* .. IRMODE = 0x0 */
-       /* .. ==> 0XE0001004[11:11] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-       /* .. UCLKEN = 0x0 */
-       /* .. ==> 0XE0001004[10:10] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-       /* .. CHMODE = 0x0 */
-       /* .. ==> 0XE0001004[9:8] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-       /* .. NBSTOP = 0x0 */
-       /* .. ==> 0XE0001004[7:6] = 0x00000000U */
-       /* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-       /* .. PAR = 0x4 */
-       /* .. ==> 0XE0001004[5:3] = 0x00000004U */
-       /* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-       /* .. CHRL = 0x0 */
-       /* .. ==> 0XE0001004[2:1] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-       /* .. CLKS = 0x0 */
-       /* .. ==> 0XE0001004[0:0] = 0x00000000U */
-       /* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-       /* .. */
-       EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
-       /* .. FINISH: UART REGISTERS */
        /* .. START: QSPI REGISTERS */
        /* .. Holdb_dr = 1 */
        /* .. ==> 0XE000D000[19:19] = 0x00000001U */