+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
* (C) Copyright 2013 - 2018 Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm/uclass.h>
+#include <env.h>
#include <fdtdec.h>
#include <fpga.h>
+#include <malloc.h>
#include <mmc.h>
+#include <watchdog.h>
#include <wdt.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/ps7_init_gpl.h>
DECLARE_GLOBAL_DATA_PTR;
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static xilinx_desc fpga;
-
-/* It can be done differently */
-static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
-static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
-static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
-static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
-static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
-static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
-static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
-#endif
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
-static struct udevice *watchdog_dev;
-#endif
-
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
-# if defined(CONFIG_WDT)
- /* bss is not cleared at time when watchdog_reset() is called */
- watchdog_dev = NULL;
-# endif
-
return 0;
}
#endif
int board_init(void)
{
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
- u32 idcode;
-
- idcode = zynq_slcr_get_idcode();
-
- switch (idcode) {
- case XILINX_ZYNQ_7007S:
- fpga = fpga007s;
- break;
- case XILINX_ZYNQ_7010:
- fpga = fpga010;
- break;
- case XILINX_ZYNQ_7012S:
- fpga = fpga012s;
- break;
- case XILINX_ZYNQ_7014S:
- fpga = fpga014s;
- break;
- case XILINX_ZYNQ_7015:
- fpga = fpga015;
- break;
- case XILINX_ZYNQ_7020:
- fpga = fpga020;
- break;
- case XILINX_ZYNQ_7030:
- fpga = fpga030;
- break;
- case XILINX_ZYNQ_7035:
- fpga = fpga035;
- break;
- case XILINX_ZYNQ_7045:
- fpga = fpga045;
- break;
- case XILINX_ZYNQ_7100:
- fpga = fpga100;
- break;
- }
-#endif
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
- if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
- puts("Watchdog: Not found!\n");
- } else {
- wdt_start(watchdog_dev, 0, 0);
- puts("Watchdog: Started\n");
- }
-# endif
-
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
- fpga_init();
- fpga_add(fpga_xilinx, &fpga);
-#endif
-
return 0;
}
int board_late_init(void)
{
+ int env_targets_len = 0;
+ const char *mode;
+ char *new_targets;
+ char *env_targets;
+
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
case ZYNQ_BM_QSPI:
+ mode = "qspi";
env_set("modeboot", "qspiboot");
break;
case ZYNQ_BM_NAND:
+ mode = "nand";
env_set("modeboot", "nandboot");
break;
case ZYNQ_BM_NOR:
+ mode = "nor";
env_set("modeboot", "norboot");
break;
case ZYNQ_BM_SD:
+ mode = "mmc";
env_set("modeboot", "sdboot");
break;
case ZYNQ_BM_JTAG:
+ mode = "pxe dhcp";
env_set("modeboot", "jtagboot");
break;
default:
+ mode = "";
env_set("modeboot", "");
break;
}
- return 0;
-}
+ /*
+ * One terminating char + one byte for space between mode
+ * and default boot_targets
+ */
+ env_targets = env_get("boot_targets");
+ if (env_targets)
+ env_targets_len = strlen(env_targets);
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- u32 version = zynq_get_silicon_version();
+ new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
+ if (!new_targets)
+ return -ENOMEM;
- version <<= 1;
- if (version > (PCW_SILICON_VERSION_3 << 1))
- version += 1;
+ sprintf(new_targets, "%s %s", mode,
+ env_targets ? env_targets : "");
- puts("Board: Xilinx Zynq\n");
- printf("Silicon: v%d.%d\n", version >> 1, version & 1);
-
- return 0;
-}
-#endif
-
-int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
-{
-#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
- defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
- if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
- CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
- ethaddr, 6))
- printf("I2C EEPROM MAC address read failed\n");
-#endif
+ env_set("boot_targets", new_targets);
return 0;
}
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
zynq_ddrc_init();
#else
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
zynq_ddrc_init();
return 0;
}
#endif
-
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
-# if !defined(CONFIG_SPL_BUILD)
- static ulong next_reset;
- ulong now;
-
- if (!watchdog_dev)
- return;
-
- now = timer_get_us();
-
- /* Do not reset the watchdog too often */
- if (now > next_reset) {
- wdt_reset(watchdog_dev);
- next_reset = now + 1000;
- }
-# endif
-}
-#endif
projects / oweals / u-boot.git / blobdiff