common: Drop linux/delay.h from common header

[oweals/u-boot.git] / board / tqc / tqm834x / tqm834x.c

diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index eca218c9cf003d8bb95f31678e303dba6c1ae11a..165a5433e728a449acc4cded824415769b3c76bb 100644 (file)
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -1,12 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <fdt_support.h>
+#include <init.h>
 #include <ioports.h>
+#include <log.h>
 #include <mpc83xx.h>
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
@@ -14,6 +16,7 @@
 #include <asm/mmu.h>
 #include <pci.h>
 #include <flash.h>
+#include <linux/delay.h>
 #include <mtd/cfi_flash.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -66,20 +69,20 @@ int board_early_init_r (void) {
 /**************************************************************************
  * DRAM initalization and size detection
  */
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
        long bank_size;
        long size;
        int cs;
 
        /* during size detection, set up the max DDRLAW size */
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE;
        im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
 
        /* set CS bounds to maximum size */
        for(cs = 0; cs < 4; ++cs) {
                set_cs_bounds(cs,
-                       CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+                       CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS),
                        DDR_MAX_SIZE_PER_CS);
 
                set_cs_config(cs, INITIAL_CS_CONFIG);
@@ -103,7 +106,7 @@ phys_size_t initdram (int board_type)
                debug("\nDetecting Bank%d\n", cs);
 
                bank_size = get_ddr_bank_size(cs,
-                       (long *)(CONFIG_SYS_DDR_BASE + size));
+                       (long *)(CONFIG_SYS_SDRAM_BASE + size));
                size += bank_size;
 
                debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
@@ -112,7 +115,9 @@ phys_size_t initdram (int board_type)
                if(size < DDR_MAX_SIZE_PER_CS) break;
        }
 
-       return size;
+       gd->ram_size = size;
+
+       return 0;
 }
 
 /**************************************************************************
@@ -234,8 +239,8 @@ static int detect_num_flash_banks(void)
        debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
 
        /* set OR0 and BR0 */
-       set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
-                  (-(total_size) & OR_GPCM_AM));
+       set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 |
+                  OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM));
        set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
                   (BR_MS_GPCM | BR_PS_32 | BR_V));