+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012
* Ивайло Димитров <freemangordon@abv.bg>
*
* (C) Copyright 2011-2012
- * Pali Rohár <pali.rohar@gmail.com>
+ * Pali Rohár <pali@kernel.org>
*
* (C) Copyright 2010
* Alistair Buxton <a.j.buxton@gmail.com>
*
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
*/
#include <common.h>
+#include <env.h>
#include <watchdog.h>
#include <malloc.h>
#include <twl4030.h>
OMAP_TAG_GPIO_SWITCH_CONFIG("sleep_ind", 0xa2, 0x2, 0x2, 0x0),
OMAP_TAG_GPIO_SWITCH_CONFIG("slide", GPIO_SLIDE, 0x0, 0x0, 0x0),
OMAP_TAG_WLAN_CX3110X_CONFIG(0x25, 0xff, 87, 42, -1),
- OMAP_TAG_PARTITION_CONFIG(PART1_NAME, PART1_SIZE * PART1_MULL,
- PART1_OFFS, PART1_MASK),
- OMAP_TAG_PARTITION_CONFIG(PART2_NAME, PART2_SIZE * PART2_MULL,
- PART2_OFFS, PART2_MASK),
- OMAP_TAG_PARTITION_CONFIG(PART3_NAME, PART3_SIZE * PART3_MULL,
- PART3_OFFS, PART3_MASK),
- OMAP_TAG_PARTITION_CONFIG(PART4_NAME, PART4_SIZE * PART4_MULL,
- PART4_OFFS, PART4_MASK),
- OMAP_TAG_PARTITION_CONFIG(PART5_NAME, PART5_SIZE * PART5_MULL,
- PART5_OFFS, PART5_MASK),
- OMAP_TAG_PARTITION_CONFIG(PART6_NAME, PART6_SIZE * PART6_MULL,
- PART6_OFFS, PART6_MASK),
+ OMAP_TAG_PARTITION_CONFIG("bootloader", 128 * 1024, 0x00000000, 0x00000003),
+ OMAP_TAG_PARTITION_CONFIG("config", 384 * 1024, 0x00020000, 0x00000000),
+ OMAP_TAG_PARTITION_CONFIG("log", 256 * 1024, 0x00080000, 0x00000000),
+ OMAP_TAG_PARTITION_CONFIG("kernel", 2 * 1024*1024, 0x000c0000, 0x00000000),
+ OMAP_TAG_PARTITION_CONFIG("initfs", 2 * 1024*1024, 0x002c0000, 0x00000000),
+ OMAP_TAG_PARTITION_CONFIG("rootfs", 257280 * 1024, 0x004c0000, 0x00000000),
OMAP_TAG_BOOT_REASON_CONFIG("pwr_key"),
OMAP_TAG_VERSION_STR_CONFIG("product", "RX-51"),
OMAP_TAG_VERSION_STR_CONFIG("hw-build", "2101"),
static char *hw_build_ptr;
static char *nolo_version_ptr;
static char *boot_mode_ptr;
+static int serial_was_console_enabled;
/*
* Routine: init_omap_tags
strcpy(boot_mode_ptr, version);
}
break;
+ case OMAP_TAG_UART:
+ if (!t->u.uart.enabled_uarts)
+ serial_was_console_enabled = 1;
+ break;
+ case OMAP_TAG_SERIAL_CONSOLE:
+ serial_was_console_enabled = 1;
+ break;
default:
break;
}
params->u.core.rootdev = 0x0;
/* append omap atag only if env setup_omap_atag is set to 1 */
- str = getenv("setup_omap_atag");
+ str = env_get("setup_omap_atag");
if (!str || str[0] != '1')
return;
- str = getenv("setup_console_atag");
- if (str && str[0] == '1')
- setup_console_atag = 1;
- else
- setup_console_atag = 0;
+ str = env_get("setup_console_atag");
+ if (str && str[0]) {
+ if (str[0] == '1')
+ setup_console_atag = 1;
+ else
+ setup_console_atag = 0;
+ } else {
+ if (serial_was_console_enabled)
+ setup_console_atag = 1;
+ else
+ setup_console_atag = 0;
+ }
- setup_boot_reason_atag = getenv("setup_boot_reason_atag");
- setup_boot_mode_atag = getenv("setup_boot_mode_atag");
+ setup_boot_reason_atag = env_get("setup_boot_reason_atag");
+ setup_boot_mode_atag = env_get("setup_boot_mode_atag");
params = *in_params;
t = (struct tag_omap *)¶ms->u;
static void twl4030_regulator_set_mode(u8 id, u8 mode)
{
u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode);
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg >> 8,
- TWL4030_PM_MASTER_PB_WORD_MSB);
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg & 0xff,
- TWL4030_PM_MASTER_PB_WORD_LSB);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PB_WORD_MSB, msg >> 8);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PB_WORD_LSB, msg & 0xff);
}
static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
+void omap3_set_aux_cr_secure(u32 acr)
+{
+ struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+
+ emu_romcode_params.num_params = 2;
+ emu_romcode_params.param1 = acr;
+
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
+}
+
/*
* Routine: omap3_update_aux_cr_secure_rx51
* Description: Modify the contents Auxiliary Control Register.
*/
static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
{
- struct emu_hal_params_rx51 emu_romcode_params = { 0, };
u32 acr;
/* Read ACR */
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
-
- emu_romcode_params.num_params = 2;
- emu_romcode_params.param1 = acr;
-
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
- (u32 *)&emu_romcode_params);
+ omap3_set_aux_cr_secure(acr);
}
/*
TWL4030_PM_RECEIVER_DEV_GRP_P1);
/* store I2C access state */
- twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &state,
- TWL4030_PM_MASTER_PB_CFG);
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+ &state);
/* enable I2C access to powerbus (needed for twl4030 regulator) */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x02,
- TWL4030_PM_MASTER_PB_CFG);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+ 0x02);
/* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */
twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE);
twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE);
/* restore I2C access state */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, state,
- TWL4030_PM_MASTER_PB_CFG);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+ state);
/* set env variable attkernaddr for relocated kernel */
sprintf(buf, "%#x", KERNEL_ADDRESS);
- setenv("attkernaddr", buf);
+ env_set("attkernaddr", buf);
/* initialize omap tags */
init_omap_tags();
/* reuse atags from previous bootloader */
reuse_atags();
- dieid_num_r();
+ omap_die_id_display();
print_cpuinfo();
/*
* Cortex-A8(r1p0..r1p2) errata 430973 workaround
* Set IBE bit in Auxiliary Control Register
+ *
+ * Call this routine only on real secure device
+ * Qemu does not implement secure PPA and crash
*/
- omap3_update_aux_cr_secure_rx51(1 << 6, 0);
+ if (get_device_type() == HS_DEVICE)
+ omap3_update_aux_cr_secure_rx51(1 << 6, 0);
return 0;
}
return;
/* read actual watchdog timeout */
- twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &timeout,
- TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_WATCHDOG_CFG, &timeout);
/* timeout 0 means watchdog is disabled */
/* reset watchdog timeout to 31s (maximum) */
if (timeout != 0)
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 31,
- TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_WATCHDOG_CFG, 31);
/* store last watchdog reset time */
twl_wd_time = get_timer(0);
{
int ret = 0;
u8 ctrl;
- ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl,
- TWL4030_KEYPAD_KEYP_CTRL_REG);
+ ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_CTRL_REG, &ctrl);
if (ret)
return ret;
ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON;
ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST;
ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN;
- ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl,
- TWL4030_KEYPAD_KEYP_CTRL_REG);
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_CTRL_REG, ctrl);
/* enable key event status */
- ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0xfe,
- TWL4030_KEYPAD_KEYP_IMR1);
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_IMR1, 0xfe);
/* enable interrupt generation on rising and falling */
/* this is a workaround for qemu twl4030 emulation */
- ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x57,
- TWL4030_KEYPAD_KEYP_EDR);
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_EDR, 0x57);
/* enable ISR clear on read */
- ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x05,
- TWL4030_KEYPAD_KEYP_SIH_CTRL);
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_SIH_CTRL, 0x05);
return 0;
}
* Routine: rx51_kp_tstc
* Description: Test if key was pressed (from buffer).
*/
-int rx51_kp_tstc(void)
+int rx51_kp_tstc(struct stdio_dev *sdev)
{
u8 c, r, dk, i;
u8 intr;
for (i = 0; i < 2; i++) {
/* check interrupt register for events */
- twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &intr,
- TWL4030_KEYPAD_KEYP_ISR1+(2*i));
+ twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_ISR1 + (2 * i), &intr);
/* no event */
if (!(intr&1))
* Routine: rx51_kp_getc
* Description: Get last pressed key (from buffer).
*/
-int rx51_kp_getc(void)
+int rx51_kp_getc(struct stdio_dev *sdev)
{
keybuf_head %= KEYBUF_SIZE;
- while (!rx51_kp_tstc())
+ while (!rx51_kp_tstc(sdev))
WATCHDOG_RESET();
return keybuf[keybuf_head++];
}
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+ twl4030_power_mmc_init(1);
+}
projects / oweals / u-boot.git / blobdiff