common: Drop linux/delay.h from common header

[oweals/u-boot.git] / board / imgtec / malta / malta.c

diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 78c4bd4efe7114767e9c52ef07a42c6fe8c1460c..88a1a63bf48866d15a43ee35faf3bf06f7bcf014 100644 (file)
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -1,17 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  * Copyright (C) 2013 Imagination Technologies
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #include <common.h>
+#include <ide.h>
+#include <init.h>
+#include <net.h>
 #include <netdev.h>
 #include <pci.h>
 #include <pci_gt64120.h>
 #include <pci_msc01.h>
 #include <rtc.h>
-#include <serial.h>
+#include <linux/delay.h>
 
 #include <asm/addrspace.h>
 #include <asm/io.h>
@@ -19,6 +21,8 @@
 
 #include "superio.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 enum core_card {
        CORE_UNKNOWN,
        CORE_LV,
@@ -52,8 +56,9 @@ static void malta_lcd_puts(const char *str)
 static enum core_card malta_core_card(void)
 {
        u32 corid, rev;
+       const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
 
-       rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
+       rev = __raw_readl(reg);
        corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
 
        switch (corid) {
@@ -82,16 +87,18 @@ static enum sys_con malta_sys_con(void)
        }
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-       return CONFIG_SYS_MEM_SIZE;
+       gd->ram_size = CONFIG_SYS_MEM_SIZE;
+
+       return 0;
 }
 
 int checkboard(void)
 {
        enum core_card core;
 
-       malta_lcd_puts("U-boot");
+       malta_lcd_puts("U-Boot");
        puts("Board: MIPS Malta");
 
        core = malta_core_card();
@@ -123,28 +130,31 @@ void _machine_restart(void)
 
        reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
        __raw_writel(GORESET, reset_base);
+       mdelay(1000);
 }
 
 int board_early_init_f(void)
 {
-       void *io_base;
+       ulong io_base;
 
        /* choose correct PCI I/O base */
        switch (malta_sys_con()) {
        case SYSCON_GT64120:
-               io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
+               io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
                break;
 
        case SYSCON_MSC01:
-               io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
+               io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
                break;
 
        default:
                return -1;
        }
 
+       set_io_port_base(io_base);
+
        /* setup FDC37M817 super I/O controller */
-       malta_superio_init(io_base);
+       malta_superio_init();
 
        return 0;
 }
@@ -156,18 +166,6 @@ int misc_init_r(void)
        return 0;
 }
 
-struct serial_device *default_serial_console(void)
-{
-       switch (malta_sys_con()) {
-       case SYSCON_GT64120:
-               return &eserial1_device;
-
-       default:
-       case SYSCON_MSC01:
-               return &eserial2_device;
-       }
-}
-
 void pci_init_board(void)
 {
        pci_dev_t bdf;
@@ -176,8 +174,6 @@ void pci_init_board(void)
 
        switch (malta_sys_con()) {
        case SYSCON_GT64120:
-               set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
-
                gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
                                 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
                                 0x10000000, 0x10000000, 128 * 1024 * 1024,
@@ -186,8 +182,6 @@ void pci_init_board(void)
 
        default:
        case SYSCON_MSC01:
-               set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
-
                msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
                               0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
                               MALTA_MSC01_PCIMEM_MAP,
@@ -217,4 +211,22 @@ void pci_init_board(void)
        pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
        val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
        pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
+
+       bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+                             PCI_DEVICE_ID_INTEL_82371AB, 0);
+       if (bdf == -1)
+               panic("Failed to find PIIX4 IDE controller\n");
+
+       /* enable bus master & IO access */
+       val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+       pci_write_config_dword(bdf, PCI_COMMAND, val32);
+
+       /* set latency */
+       pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
+
+       /* enable IDE/ATA */
+       pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
+                              PCI_CFG_PIIX4_IDETIM_IDE);
+       pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
+                              PCI_CFG_PIIX4_IDETIM_IDE);
 }