+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Timesys Corporation
* Copyright 2015 General Electric Company
* Copyright 2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <env.h>
#include <linux/errno.h>
+#include <linux/libfdt.h>
#include <asm/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
+#include <net.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <i2c.h>
#include <input.h>
#include <pwm.h>
+#include <version.h>
#include <stdlib.h>
+#include "../common/ge_common.h"
#include "../common/vpd_reader.h"
+#include "../../../drivers/net/e1000.h"
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#endif
-
-#ifndef CONFIG_SYS_I2C_EEPROM_BUS
-#define CONFIG_SYS_I2C_EEPROM_BUS 2
-#endif
+static int confidx = 3; /* Default to b850v3. */
+static struct vpd_cache vpd;
#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
/* Reset AR8033 PHY */
+ gpio_request(IMX_GPIO_NR(1, 28), "fec_rst");
gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 28), 1);
mdelay(1);
}
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
- MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
}
};
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
-}
-
-static void setup_spi(void)
-{
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-}
-#endif
-
static iomux_v3_cfg_t const pcie_pads[] = {
MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC2_BASE_ADDR},
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC3_BASE_ADDR:
- ret = 1; /* eMMC is always present */
- break;
- case USDHC4_BASE_ADDR:
- ret = !gpio_get_value(USDHC4_CD_GPIO);
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- int i;
-
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- break;
- case 2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- gpio_direction_input(USDHC4_CD_GPIO);
- usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers\n"
- "(%d) then supported by the board (%d)\n",
- i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
static int mx6_rgmii_rework(struct phy_device *phydev)
{
/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
return 0;
}
-static int detect_baseboard(struct display_info_t const *dev)
+static int is_b850v3(void)
{
- if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
- IS_ENABLED(CONFIG_TARGET_GE_B650V3))
- return 1;
+ return confidx == 3;
+}
- return 0;
+static int detect_lcd(struct display_info_t const *dev)
+{
+ return !is_b850v3();
}
struct display_info_t const displays[] = {{
.bus = -1,
.addr = -1,
.pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_baseboard,
+ .detect = detect_lcd,
.enable = NULL,
.mode = {
.name = "G121X1-L03",
setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
- /* set video pll to 910MHz (24MHz * (37+11/12))
- * video pll post div to 910/4 = 227.5MHz
- */
+ /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
+ * |
+ * PLL5
+ * |
+ * CS2CDR[LDB_DI0_CLK_SEL]
+ * |
+ * +----> LDB_DI0_SERIAL_CLK_ROOT
+ * |
+ * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
+ */
+
clrsetbits_le32(&ccm->analog_pll_video,
BM_ANADIG_PLL_VIDEO_DIV_SELECT |
BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
- BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
enable_videopll();
- /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
- clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+ /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
+ setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
imx_setup_hdmi();
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ enable_videopll();
+
/* When a reset/reboot is performed the display power needs to be turned
* off for atleast 500ms. The boot time is ~300ms, we need to wait for
* an additional 200ms here. Unfortunately we use external PMIC for
*/
mdelay(200);
- /* IPU1 DI0 clock is 480/7 = 68.5 MHz */
+ /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
/* Set LDB_DI0 as clock source for IPU_DI0 */
/* backlights off until needed */
imx_iomux_v3_setup_multiple_pads(backlight_pads,
ARRAY_SIZE(backlight_pads));
+ gpio_request(LVDS_POWER_GP, "lvds_power");
gpio_direction_input(LVDS_POWER_GP);
- gpio_direction_input(LVDS_BACKLIGHT_GP);
}
#endif /* CONFIG_VIDEO_IPUV3 */
#define VPD_PRODUCT_B850 1
#define VPD_PRODUCT_B650 2
#define VPD_PRODUCT_B450 3
+#define VPD_HAS_MAC1 0x1
+#define VPD_HAS_MAC2 0x2
+#define VPD_MAC_ADDRESS_LENGTH 6
struct vpd_cache {
- uint8_t product_id;
- uint8_t macbits;
- unsigned char mac1[6];
+ bool is_read;
+ u8 product_id;
+ u8 has;
+ unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
+ unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
};
/*
* Extracts MAC and product information from the VPD.
*/
-static int vpd_callback(
- void *userdata,
- uint8_t id,
- uint8_t version,
- uint8_t type,
- size_t size,
- uint8_t const *data)
+static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
+ size_t size, u8 const *data)
{
- struct vpd_cache *vpd = (struct vpd_cache *)userdata;
-
- if ( id == VPD_BLOCK_HWID
- && version == 1
- && type != VPD_TYPE_INVALID
- && size >= 1) {
+ if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
+ size >= 1) {
vpd->product_id = data[0];
-
- } else if ( id == VPD_BLOCK_NETWORK
- && version == 1
- && type != VPD_TYPE_INVALID
- && size >= 6) {
- vpd->macbits |= 1;
- memcpy(vpd->mac1, data, 6);
+ } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
+ type != VPD_TYPE_INVALID) {
+ if (size >= 6) {
+ vpd->has |= VPD_HAS_MAC1;
+ memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
+ }
+ if (size >= 12) {
+ vpd->has |= VPD_HAS_MAC2;
+ memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
+ }
}
return 0;
}
-static void set_eth0_mac_address(unsigned char * mac)
-{
- uint32_t *ENET_TCR = (uint32_t*)0x21880c4;
- uint32_t *ENET_PALR = (uint32_t*)0x21880e4;
- uint32_t *ENET_PAUR = (uint32_t*)0x21880e8;
-
- *ENET_TCR |= 0x100; /* ADDINS */
- *ENET_PALR |= (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
- *ENET_PAUR |= (mac[4] << 24) | (mac[5] << 16);
-}
-
static void process_vpd(struct vpd_cache *vpd)
{
- if ( vpd->product_id == VPD_PRODUCT_B850
- || vpd->product_id == VPD_PRODUCT_B650
- || vpd->product_id == VPD_PRODUCT_B450) {
- if (vpd->macbits & 1) {
- set_eth0_mac_address(vpd->mac1);
- }
+ int fec_index = -1;
+ int i210_index = -1;
+
+ if (!vpd->is_read) {
+ printf("VPD wasn't read");
+ return;
}
-}
-static int read_vpd(uint eeprom_bus)
-{
- struct vpd_cache vpd;
- int res;
- int size = 1024;
- uint8_t *data;
- unsigned int current_i2c_bus = i2c_get_bus_num();
-
- res = i2c_set_bus_num(eeprom_bus);
- if (res < 0)
- return res;
-
- data = (uint8_t *)malloc(size);
- if (!data)
- return -ENOMEM;
-
- res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size);
-
- if (res == 0) {
- memset(&vpd, 0, sizeof(vpd));
- vpd_reader(size, data, &vpd, vpd_callback);
- process_vpd(&vpd);
+ switch (vpd->product_id) {
+ case VPD_PRODUCT_B450:
+ env_set("confidx", "1");
+ i210_index = 0;
+ fec_index = 1;
+ break;
+ case VPD_PRODUCT_B650:
+ env_set("confidx", "2");
+ i210_index = 0;
+ fec_index = 1;
+ break;
+ case VPD_PRODUCT_B850:
+ env_set("confidx", "3");
+ i210_index = 1;
+ fec_index = 2;
+ break;
}
- free(data);
+ if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
+ eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
- i2c_set_bus_num(current_i2c_bus);
- return res;
+ if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
+ eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
}
int board_eth_init(bd_t *bis)
setup_iomux_enet();
setup_pcie();
+ e1000_initialize(bis);
+
return cpu_eth_init(bis);
}
MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
+ MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
};
#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
#define WIFI_EN IMX_GPIO_NR(6, 14)
setup_iomux_uart();
#if defined(CONFIG_VIDEO_IPUV3)
- if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
- /* Set LDB clock to Video PLL */
- select_ldb_di_clock_source(MXC_PLL5_CLK);
- else
- /* Set LDB clock to USB PLL */
- select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
+ /* Set LDB clock to Video PLL */
+ select_ldb_di_clock_source(MXC_PLL5_CLK);
#endif
return 0;
}
+static void set_confidx(const struct vpd_cache* vpd)
+{
+ switch (vpd->product_id) {
+ case VPD_PRODUCT_B450:
+ confidx = 1;
+ break;
+ case VPD_PRODUCT_B650:
+ confidx = 2;
+ break;
+ case VPD_PRODUCT_B850:
+ confidx = 3;
+ break;
+ }
+}
+
int board_init(void)
{
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+
+ if (!read_vpd(&vpd, vpd_callback)) {
+ vpd.is_read = true;
+ set_confidx(&vpd);
+ }
+
+ gpio_request(SUS_S3_OUT, "sus_s3_out");
gpio_direction_output(SUS_S3_OUT, 1);
+
+ gpio_request(WIFI_EN, "wifi_en");
gpio_direction_output(WIFI_EN, 1);
+
#if defined(CONFIG_VIDEO_IPUV3)
- if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+ if (is_b850v3())
setup_display_b850v3();
else
setup_display_bx50v3();
-#endif
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-#ifdef CONFIG_MXC_SPI
- setup_spi();
+ gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
+ gpio_direction_input(LVDS_BACKLIGHT_GP);
#endif
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
- setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
- read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int board_late_init(void)
{
+ process_vpd(&vpd);
+
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
+ if (is_b850v3())
+ env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
+ else
+ env_set("videoargs", "video=LVDS-1:1024x768@65");
+
+ /* board specific pmic init */
+ pmic_init();
+
+ check_time();
+
+ return 0;
+}
+
+/*
+ * Removes the 'eth[0-9]*addr' environment variable with the given index
+ *
+ * @param index [in] the index of the eth_device whose variable is to be removed
+ */
+static void remove_ethaddr_env_var(int index)
+{
+ char env_var_name[9];
+
+ sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
+ env_set(env_var_name, NULL);
+}
+
+int last_stage_init(void)
+{
+ int i;
+
+ /*
+ * Remove first three ethaddr which may have been created by
+ * function process_vpd().
+ */
+ for (i = 0; i < 3; ++i)
+ remove_ethaddr_env_var(i);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("BOARD: %s\n", CONFIG_BOARD_NAME);
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ fdt_setprop(blob, 0, "ge,boot-ver", version_string,
+ strlen(version_string) + 1);
+ return 0;
+}
+#endif
+
+static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
#ifdef CONFIG_VIDEO_IPUV3
/* We need at least 200ms between power on and backlight on
* as per specifications from CHI MEI */
pwm_enable(0);
#endif
- /* board specific pmic init */
- pmic_init();
-
return 0;
}
-int checkboard(void)
-{
- printf("BOARD: %s\n", CONFIG_BOARD_NAME);
- return 0;
-}
+U_BOOT_CMD(
+ bx50_backlight_enable, 1, 1, do_backlight_enable,
+ "enable Bx50 backlight",
+ ""
+);
projects / oweals / u-boot.git / blobdiff