+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
*/
#include <common.h>
#include <command.h>
+#include <env.h>
+#include <init.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
-#include <libfdt.h>
+#include <linux/libfdt.h>
#include <fdt_support.h>
+#include <fsl_mdio.h>
#include <tsec.h>
#include <asm/fsl_law.h>
#include <netdev.h>
#include "../common/ngpixis.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Set pmuxcr to allow both i2c1 and i2c2 */
setbits_be32(&gur->pmuxcr, 0x1000);
+#ifdef CONFIG_SYS_RAMBOOT
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+#endif
/* Read back the register to synchronize the write. */
in_be32(&gur->pmuxcr);
/* Set the pin muxing to enable ETSEC2. */
clrbits_be32(&gur->pmuxcr2, 0x001F8000);
+ /* Enable the SPI */
+ clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
+
return 0;
}
{
u8 sw;
- puts("Board: P1022DS ");
-#ifdef CONFIG_PHYS_64BIT
- puts("(36-bit addrmap) ");
-#endif
-
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ printf("Board: P1022DS Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
/* Choose the 11.2896Mhz codec reference clock */
#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
+/* Connect to USB2 */
+#define CONFIG_PIXIS_BRDCFG0_USB2 0x10
+/* Connect to TFM bus */
+#define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
+/* Connect to SPI */
+#define CONFIG_PIXIS_BRDCFG0_SPI 0x80
+
int misc_init_r(void)
{
u8 temp;
const char *audclk;
size_t arglen;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* For DVI, enable the TFP410 Encoder. */
return -1;
debug("DVI Encoder Read: 0x%02x\n",temp);
+ /* Enable the USB2 in PMUXCR2 and FGPA */
+ if (hwconfig("usb2")) {
+ clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
+ MPC85xx_PMUXCR2_USB);
+ setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
+ }
+
+ /* tdm and audio can not enable simultaneous*/
+ if (hwconfig("tdm") && hwconfig("audclk")){
+ printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
+ return -1;
+ }
+
+ /* Enable the TDM in PMUXCR and FGPA */
+ if (hwconfig("tdm")) {
+ clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
+ MPC85xx_PMUXCR_TDM);
+ setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
+ /* TDM need some configration option by SPI */
+ clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
+ MPC85xx_PMUXCR_SPI);
+ setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
+ }
+
/*
* Enable the reference clock for the WM8776 codec, and route the MUX
* pins for SSI. The default is the 12.288 MHz clock
*/
- temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
- CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
- temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
-
- audclk = hwconfig_arg("audclk", &arglen);
- /* Check the first two chars only */
- if (audclk && (strncmp(audclk, "11", 2) == 0))
- temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
- else
- temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
- out_8(&pixis->brdcfg1, temp);
+ if (hwconfig("audclk")) {
+ temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+ CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+ temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ /* Check the first two chars only */
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+ else
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+ setbits_8(&pixis->brdcfg1, temp);
+ }
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
flush_dcache();
invalidate_icache();
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
*/
int board_eth_init(bd_t *bis)
{
+ struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[2];
unsigned int num = 0;
num++;
#endif
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
}
* ft_codec_setup - fix up the clock-frequency property of the codec node
*
* Update the clock-frequency property based on the value of the 'audclk'
- * hwconfig option. If audclk is not specified, then default to 12.288MHz.
+ * hwconfig option. If audclk is not specified, then don't write anything
+ * to the device tree, because it means that the codec clock is disabled.
*/
static void ft_codec_setup(void *blob, const char *compatible)
{
u32 freq;
audclk = hwconfig_arg("audclk", &arglen);
- if (audclk && (strncmp(audclk, "11", 2) == 0))
- freq = 11289600;
- else
- freq = 12288000;
-
- do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+ if (audclk) {
+ if (strncmp(audclk, "11", 2) == 0)
+ freq = 11289600;
+ else
+ freq = 12288000;
+
+ do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
+ freq, 1);
+ }
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
- base = getenv_bootm_low();
- size = getenv_bootm_size();
+ base = env_get_bootm_low();
+ size = env_get_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER
/* Update the WM8776 node's clock frequency property */
ft_codec_setup(blob, "wlf,wm8776");
+
+ return 0;
}
#endif