+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright 2020 NXP
*/
#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <init.h>
+#include <net.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
+#include <env.h>
#include <miiphy.h>
-#include <libfdt.h>
+#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
return 0;
}
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u8 tmp;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ int ret;
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
+ I2C_PCA9557_ADDR1, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n",
+ __func__, I2C_PCA9557_BUS_NUM);
+ return ret;
+ }
+ switch (ctrl_type) {
+ case MUX_TYPE_IFC:
+ tmp = 0xf0;
+ dm_i2c_write(dev, 3, &tmp, 1);
+ tmp = 0x01;
+ dm_i2c_write(dev, 1, &tmp, 1);
+ sd_ifc_mux = MUX_TYPE_IFC;
+ clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+ break;
+ case MUX_TYPE_SDHC:
+ tmp = 0xf0;
+ dm_i2c_write(dev, 3, &tmp, 1);
+ tmp = 0x05;
+ dm_i2c_write(dev, 1, &tmp, 1);
+ sd_ifc_mux = MUX_TYPE_SDHC;
+ clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+ PMUXCR1_SDHC_ENABLE);
+ break;
+ case MUX_TYPE_SPIFLASH:
+ out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+ break;
+ case MUX_TYPE_TDM:
+ out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
+ out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+ break;
+ case MUX_TYPE_CAN:
+ out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+ break;
+ default:
+ break;
+ }
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+ ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
+ I2C_PCA9557_ADDR2, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n",
+ __func__, I2C_PCA9557_BUS_NUM);
+ return ret;
+ }
+ switch (ctrl_type) {
+ case MUX_TYPE_IFC:
+ dm_i2c_read(dev, 0, &tmp, 1);
+ clrbits_8(&tmp, 0x04);
+ dm_i2c_write(dev, 1, &tmp, 1);
+ dm_i2c_read(dev, 3, &tmp, 1);
+ clrbits_8(&tmp, 0x04);
+ dm_i2c_write(dev, 3, &tmp, 1);
+ sd_ifc_mux = MUX_TYPE_IFC;
+ clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+ break;
+ case MUX_TYPE_SDHC:
+ dm_i2c_read(dev, 0, &tmp, 1);
+ setbits_8(&tmp, 0x04);
+ dm_i2c_write(dev, 1, &tmp, 1);
+ dm_i2c_read(dev, 3, &tmp, 1);
+ clrbits_8(&tmp, 0x04);
+ dm_i2c_write(dev, 3, &tmp, 1);
+ sd_ifc_mux = MUX_TYPE_SDHC;
+ clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+ PMUXCR1_SDHC_ENABLE);
+ break;
+ case MUX_TYPE_SPIFLASH:
+ dm_i2c_read(dev, 0, &tmp, 1);
+ clrbits_8(&tmp, 0x80);
+ dm_i2c_write(dev, 1, &tmp, 1);
+ dm_i2c_read(dev, 3, &tmp, 1);
+ clrbits_8(&tmp, 0x80);
+ dm_i2c_write(dev, 3, &tmp, 1);
+ break;
+ case MUX_TYPE_TDM:
+ dm_i2c_read(dev, 0, &tmp, 1);
+ setbits_8(&tmp, 0x82);
+ dm_i2c_write(dev, 1, &tmp, 1);
+ dm_i2c_read(dev, 3, &tmp, 1);
+ clrbits_8(&tmp, 0x82);
+ dm_i2c_write(dev, 3, &tmp, 1);
+ break;
+ case MUX_TYPE_CAN:
+ dm_i2c_read(dev, 0, &tmp, 1);
+ clrbits_8(&tmp, 0x02);
+ dm_i2c_write(dev, 1, &tmp, 1);
+ dm_i2c_read(dev, 3, &tmp, 1);
+ clrbits_8(&tmp, 0x02);
+ dm_i2c_write(dev, 3, &tmp, 1);
+ break;
+ case MUX_TYPE_CS0_NOR:
+ dm_i2c_read(dev, 0, &tmp, 1);
+ clrbits_8(&tmp, 0x08);
+ dm_i2c_write(dev, 1, &tmp, 1);
+ dm_i2c_read(dev, 3, &tmp, 1);
+ clrbits_8(&tmp, 0x08);
+ dm_i2c_write(dev, 3, &tmp, 1);
+ break;
+ case MUX_TYPE_CS0_NAND:
+ dm_i2c_read(dev, 0, &tmp, 1);
+ setbits_8(&tmp, 0x08);
+ dm_i2c_write(dev, 1, &tmp, 1);
+ dm_i2c_read(dev, 3, &tmp, 1);
+ clrbits_8(&tmp, 0x08);
+ dm_i2c_write(dev, 3, &tmp, 1);
+ break;
+ default:
+ break;
+ }
+#endif
+#else
#if defined(CONFIG_TARGET_P1010RDB_PA)
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
break;
}
i2c_set_bus_num(orig_bus);
+#endif
#endif
return 0;
}
int i2c_pca9557_read(int type)
{
u8 val;
+ int bus_num = I2C_PCA9557_BUS_NUM;
- i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n",
+ __func__, bus_num);
+ return ret;
+ }
+ dm_i2c_read(dev, 0, &val, 1);
+#else
+ i2c_set_bus_num(bus_num);
i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
+#endif
switch (type) {
case I2C_READ_BANK:
printf("Board: %sRDB-PA, ", cpu->name);
#elif defined(CONFIG_TARGET_P1010RDB_PB)
printf("Board: %sRDB-PB, ", cpu->name);
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ I2C_PCA9557_BUS_NUM);
+ return ret;
+ }
+ val = 0x0; /* no polarity inversion */
+ dm_i2c_write(dev, 2, &val, 1);
+#else
i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
val = 0x0; /* no polarity inversion */
i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
#endif
+#endif
#ifdef CONFIG_SDCARD
/* switch to IFC to read info from CPLD */
case 0xe:
puts("SDHC\n");
val = 0x60; /* set pca9557 pin input/output */
+#ifdef CONFIG_DM_I2C
+ dm_i2c_write(dev, 3, &val, 1);
+#else
i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
+#endif
break;
case 0x5:
config_board_mux(MUX_TYPE_IFC);
base = env_get_bootm_low();
size = env_get_bootm_size();
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
FT_FSL_PCI_SETUP;
#endif
return 0;
}
-static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+#ifndef CONFIG_SPL_BUILD
+static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
{
if (argc < 2)
return CMD_RET_USAGE;
"configure multiplexing pin for IFC/SDHC bus in runtime",
"bus_type (e.g. mux sdhc)"
);
+#endif
projects / oweals / u-boot.git / blobdiff