+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
#include <i2c.h>
#include <asm/io.h>
-#include <libfdt.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <netdev.h>
-#include "../common/pixis.h"
+DECLARE_GLOBAL_DATA_PTR;
void sdram_init(void);
phys_size_t fixed_sdram(void);
-void mpc8610hpcd_diu_init(void);
+int mpc8610hpcd_diu_init(void);
/* called before any console output */
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
tmp_val = 0x10;
i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
-
-#ifdef CONFIG_FSL_DIU_FB
- mpc8610hpcd_diu_init();
-#endif
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
return 0;
}
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
u8 *pixis_base = (u8 *)PIXIS_BASE;
- printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
- "System Version: 0x%02x, FPGA Version: 0x%02x\n",
+ printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
+ /*
+ * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
+ * bank and LBMAP=00 is the alternate bank. However, the pixis
+ * altbank code can only set bits, not clear them, so we treat 00 as
+ * the normal bank and 11 as the alternate.
+ */
+ switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
+ case 0:
+ puts("vBank: Standard\n");
+ break;
+ case 0x40:
+ puts("Promjet\n");
+ break;
+ case 0x80:
+ puts("NAND\n");
+ break;
+ case 0xC0:
+ puts("vBank: Alternate\n");
+ break;
+ }
+
mcm->abcr |= 0x00010000; /* 0 */
mcm->hpmr3 = 0x80000008; /* 4c */
mcm->hpmr0 = 0;
}
-phys_size_t
-initdram(int board_type)
+int dram_init(void)
{
phys_size_t dram_size = 0;
setup_ddr_bat(dram_size);
- puts(" DDR: ");
- return dram_size;
+ debug(" DDR: ");
+ gd->ram_size = dram_size;
+
+ return 0;
}
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
uint d_init;
ddr->cs0_bnds = 0x0000001f;
#endif
-static struct pci_controller pci1_hose = {
-#ifndef CONFIG_PCI_PNP
-config_table:pci_mpc86xxcts_config_table
-#endif
-};
+static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI */
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
- struct fsl_pci_info pci_info[3];
- u32 devdisr, pordevsr, io_sel;
- int first_free_busno = 0;
- int num = 0;
-
- int pci_agent, pcie_ep, pcie_configured;
+ struct fsl_pci_info pci_info;
+ u32 devdisr;
+ int first_free_busno;
+ int pci_agent;
devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL)
- >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
-
- debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
-#ifdef CONFIG_PCIE1
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
- SET_STD_PCIE_INFO(pci_info[num], 1);
- pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
-
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
- } else {
- printf (" PCIE1: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
-
- if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
- SET_STD_PCIE_INFO(pci_info[num], 2);
- pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
- } else {
- printf (" PCIE2: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
-#endif
+ first_free_busno = fsl_pcie_init_board(0);
#ifdef CONFIG_PCI1
if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info[num], 1);
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
- printf(" PCI connected to PCI slots as %s" \
+ SET_STD_PCI_INFO(pci_info, 1);
+ set_next_law(pci_info.mem_phys,
+ law_size_bits(pci_info.mem_size), pci_info.law);
+ set_next_law(pci_info.io_phys,
+ law_size_bits(pci_info.io_size), pci_info.law);
+
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+ printf("PCI: connected to PCI slots as %s" \
" (base address %lx)\n",
pci_agent ? "Agent" : "Host",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ pci_info.regs);
+#ifndef CONFIG_PCI_PNP
+ pci1_hose.config_table = pci_mpc86xxcts_config_table;
+#endif
+ first_free_busno = fsl_pci_init_port(&pci_info,
&pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf("PCI: disabled\n");
}
puts("\n");
#else
setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
#endif
+
+ fsl_pcie_init_board(first_free_busno);
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
-#endif
+ FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
projects / oweals / u-boot.git / blobdiff