common: Drop linux/delay.h from common header

[oweals/u-boot.git] / board / freescale / mpc8555cds / mpc8555cds.c

diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index b7e0e0cd82bad2b5ac08137b116b1353c726b14f..8e27e73c25c986c36c6bce325f16feb7a71d7c48 100644 (file)
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -1,34 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Copyright 2004, 2011 Freescale Semiconductor.
  */
 
 #include <common.h>
+#include <init.h>
 #include <pci.h>
+#include <vsprintf.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <spd_sdram.h>
-#include <libfdt.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
 #include <fdt_support.h>
 
 #include "../common/cadmus.h"
@@ -40,7 +26,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
 void local_bus_init(void);
-void sdram_init(void);
 
 /*
  * I/O Port configuration table
@@ -199,6 +184,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
 int checkboard (void)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       char buf[32];
 
        /* PCI slot in USER bits CSR[6:7] by convention. */
        uint pci_slot = get_pci_slot ();
@@ -219,17 +205,16 @@ int checkboard (void)
                MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
                MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
 
-       printf ("    PCI1: %d bit, %s MHz, %s\n",
+       printf("PCI1: %d bit, %s MHz, %s\n",
                (pci1_32) ? 32 : 64,
-               (pci1_speed == 33000000) ? "33" :
-               (pci1_speed == 66000000) ? "66" : "unknown",
+               strmhz(buf, pci1_speed),
                pci1_clk_sel ? "sync" : "async");
 
        if (pci_dual) {
-               printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+               printf("PCI2: 32 bit, 66 MHz, %s\n",
                        pci2_clk_sel ? "sync" : "async");
        } else {
-               printf ("    PCI2: disabled\n");
+               printf("PCI2: disabled\n");
        }
 
        /*
@@ -240,50 +225,6 @@ int checkboard (void)
        return 0;
 }
 
-phys_size_t
-initdram(int board_type)
-{
-       long dram_size = 0;
-
-       puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
-       {
-               /*
-                * Work around to stabilize DDR DLL MSYNC_IN.
-                * Errata DDR9 seems to have been fixed.
-                * This is now the workaround for Errata DDR11:
-                *    Override DLL = 1, Course Adj = 1, Tap Select = 0
-                */
-
-               volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
-               gur->ddrdllcr = 0x81000000;
-               asm("sync;isync;msync");
-               udelay(200);
-       }
-#endif
-
-       dram_size = fsl_ddr_sdram();
-       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-       dram_size *= 0x100000;
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
-
-       /*
-        * SDRAM Initialization
-        */
-       sdram_init();
-
-       puts("    DDR: ");
-       return dram_size;
-}
-
 /*
  * Initialize Local Bus
  */
@@ -309,16 +250,16 @@ local_bus_init(void)
 
        get_sys_info(&sysinfo);
        clkdiv = lbc->lcrr & LCRR_CLKDIV;
-       lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+       lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
 
        if (lbc_hz < 66) {
-               lbc->lcrr |= 0x80000000;        /* DLL Bypass */
+               lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
 
        } else if (lbc_hz >= 133) {
-               lbc->lcrr &= (~0x80000000);             /* DLL Enabled */
+               lbc->lcrr &= (~LCRR_DBYP);              /* DLL Enabled */
 
        } else {
-               lbc->lcrr &= (~0x8000000);      /* DLL Enabled */
+               lbc->lcrr &= (~LCRR_DBYP);      /* DLL Enabled */
                udelay(200);
 
                /*
@@ -334,8 +275,7 @@ local_bus_init(void)
 /*
  * Initialize SDRAM memory on the Local Bus.
  */
-void
-sdram_init(void)
+void lbc_sdram_init(void)
 {
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
@@ -345,9 +285,9 @@ sdram_init(void)
        uint cpu_board_rev;
        uint lsdmr_common;
 
-       puts("    SDRAM: ");
-
-       print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+       puts("LBC SDRAM: ");
+       print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+                  "\n       ");
 
        /*
         * Setup SDRAM Base and Option Registers