common: Drop linux/delay.h from common header

[oweals/u-boot.git] / board / freescale / mpc8315erdb / sdram.c

diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
index f97e3c78043ed139ae6b6dc0277566c3ee8060ea..8a828207f9356eed3c11f0403e6fd4a813b4031d 100644 (file)
--- a/board/freescale/mpc8315erdb/sdram.c
+++ b/board/freescale/mpc8315erdb/sdram.c
@@ -1,32 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2007 Freescale Semiconductor, Inc.
  *
  * Authors: Nick.Spence@freescale.com
  *          Wilson.Lo@freescale.com
  *          scottwood@freescale.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #include <common.h>
+#include <init.h>
 #include <mpc83xx.h>
 #include <spd_sdram.h>
+#include <linux/delay.h>
 
 #include <asm/bitops.h>
 #include <asm/io.h>
@@ -54,44 +39,45 @@ static void resume_from_sleep(void)
  * This is useful for faster booting in configs where the RAM is unlikely
  * to be changed, or for things like NAND booting where space is tight.
  */
+#ifndef CONFIG_SYS_RAMBOOT
 static long fixed_sdram(void)
 {
-       volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
-       u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+       volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+       u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
        u32 msize_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE  & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-       im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+       im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 
        /*
         * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
         * or the DDR2 controller may fail to initialize correctly.
         */
-       udelay(50000);
+       __udelay(50000);
 
        im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-       im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 
        /* Currently we use only one CS, so disable the other bank. */
        im->ddr.cs_config[1] = 0;
 
-       im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
-       im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-       im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-       im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-       im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+       im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+       im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+       im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+       im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+       im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 
        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-               im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG | SDRAM_CFG_BI;
+               im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
        else
-               im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+               im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 
-       im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-       im->ddr.sdram_mode = CFG_DDR_MODE;
-       im->ddr.sdram_mode2 = CFG_DDR_MODE2;
+       im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+       im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+       im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 
-       im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+       im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
        sync();
 
        /* enable DDR controller */
@@ -100,14 +86,20 @@ static long fixed_sdram(void)
 
        return msize;
 }
+#else
+static long fixed_sdram(void)
+{
+       return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
 
-long int initdram(int board_type)
+int dram_init(void)
 {
-       volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+       volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
        u32 msize;
 
        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-               return -1;
+               return -ENXIO;
 
        /* DDR SDRAM */
        msize = fixed_sdram();
@@ -115,6 +107,8 @@ long int initdram(int board_type)
        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
                resume_from_sleep();
 
-       /* return total bus SDRAM size(bytes)  -- DDR */
-       return msize;
+       /* set total bus SDRAM size(bytes)  -- DDR */
+       gd->ram_size = msize;
+
+       return 0;
 }