// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*/
#include <common.h>
+#include <clock_legacy.h>
#include <dm.h>
#include <dm/platform_data/serial_pl01x.h>
#include <i2c.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <efi_loader.h>
#include <asm/arch/mmu.h>
#include <hwconfig.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/config.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include "../common/qixis.h"
#include "../common/vid.h"
#include <fsl_immap.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#ifdef CONFIG_EMC2305
#include "../common/emc2305.h"
{
int ret;
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
return 0;
}
+#ifdef CONFIG_OF_BOARD_FIXUP
+int board_fix_fdt(void *fdt)
+{
+ char *reg_names, *reg_name;
+ int names_len, old_name_len, new_name_len, remaining_names_len;
+ struct str_map {
+ char *old_str;
+ char *new_str;
+ } reg_names_map[] = {
+ { "ccsr", "dbi" },
+ { "pf_ctrl", "ctrl" }
+ };
+ int off = -1, i = 0;
+
+ if (IS_SVR_REV(get_svr(), 1, 0))
+ return 0;
+
+ off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
+ while (off != -FDT_ERR_NOTFOUND) {
+ fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
+ strlen("fsl,ls-pcie") + 1);
+
+ reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
+ &names_len);
+ if (!reg_names)
+ continue;
+
+ reg_name = reg_names;
+ remaining_names_len = names_len - (reg_name - reg_names);
+ i = 0;
+ while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
+ old_name_len = strlen(reg_names_map[i].old_str);
+ new_name_len = strlen(reg_names_map[i].new_str);
+ if (memcmp(reg_name, reg_names_map[i].old_str,
+ old_name_len) == 0) {
+ /* first only leave required bytes for new_str
+ * and copy rest of the string after it
+ */
+ memcpy(reg_name + new_name_len,
+ reg_name + old_name_len,
+ remaining_names_len - old_name_len);
+ /* Now copy new_str */
+ memcpy(reg_name, reg_names_map[i].new_str,
+ new_name_len);
+ names_len -= old_name_len;
+ names_len += new_name_len;
+ i++;
+ }
+
+ reg_name = memchr(reg_name, '\0', remaining_names_len);
+ if (!reg_name)
+ break;
+
+ reg_name += 1;
+
+ remaining_names_len = names_len -
+ (reg_name - reg_names);
+ }
+
+ fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
+ off = fdt_node_offset_by_compatible(fdt, off,
+ "fsl,lx2160a-pcie");
+ }
+
+ return 0;
+}
+#endif
+
#if defined(CONFIG_TARGET_LX2160AQDS)
void esdhc_dspi_status_fixup(void *blob)
{
const char esdhc0_path[] = "/soc/esdhc@2140000";
const char esdhc1_path[] = "/soc/esdhc@2150000";
- const char dspi0_path[] = "/soc/dspi@2100000";
- const char dspi1_path[] = "/soc/dspi@2110000";
- const char dspi2_path[] = "/soc/dspi@2120000";
+ const char dspi0_path[] = "/soc/spi@2100000";
+ const char dspi1_path[] = "/soc/spi@2110000";
+ const char dspi2_path[] = "/soc/spi@2120000";
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 sdhc1_base_pmux;
& FSL_CHASSIS3_IIC5_PMUX_MASK;
iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
- if (iic5_pmux == IIC5_PMUX_SPI3) {
+ if (iic5_pmux == IIC5_PMUX_SPI3)
do_fixup_by_path(blob, dspi2_path, "status", "okay",
sizeof("okay"), 1);
- }
+ else
+ do_fixup_by_path(blob, dspi2_path, "status", "disabled",
+ sizeof("disabled"), 1);
}
#endif
int init_func_vid(void)
{
- if (adjust_vdd(0) < 0)
+ int set_vid;
+
+ if (IS_SVR_REV(get_svr(), 1, 0))
+ set_vid = adjust_vdd(800);
+ else
+ set_vid = adjust_vdd(0);
+
+ if (set_vid < 0)
printf("core voltage not adjusted\n");
return 0;
if (src == BOOT_SOURCE_SD_MMC) {
puts("SD\n");
+ } else if (src == BOOT_SOURCE_SD_MMC2) {
+ puts("eMMC\n");
} else {
sw = QIXIS_READ(brdcfg[0]);
sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
- puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
+ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
#endif
return 0;
}
reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
QIXIS_WRITE(brdcfg[11], reg11);
} else {
- /* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
+ /*
+ * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
+ * do not change it.
+ * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
+ */
reg11 = QIXIS_READ(brdcfg[11]);
- reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
- QIXIS_WRITE(brdcfg[11], reg11);
+ if ((reg11 & 0x30) != 0x30) {
+ reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
+ QIXIS_WRITE(brdcfg[11], reg11);
+ }
/* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
* {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
return 0;
}
+#elif defined(CONFIG_TARGET_LX2160ARDB)
+int config_board_mux(void)
+{
+ u8 brdcfg;
+
+ brdcfg = QIXIS_READ(brdcfg[4]);
+ /* The BRDCFG4 register controls general board configuration.
+ *|-------------------------------------------|
+ *|Field | Function |
+ *|-------------------------------------------|
+ *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
+ *|CAN_EN | 0= CAN transceivers are disabled. |
+ *| | 1= CAN transceivers are enabled. |
+ *|-------------------------------------------|
+ */
+ brdcfg |= BIT_MASK(5);
+ QIXIS_WRITE(brdcfg[4], brdcfg);
+
+ return 0;
+}
#else
int config_board_mux(void)
{
sec_init();
#endif
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+ pci_init();
+#endif
return 0;
}
print_ddr_info(0);
}
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
{
config_board_mux();
return;
}
- if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) {
+ if (get_mc_boot_status() == 0 &&
+ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
fdt_status_okay(fdt, offset);
+#ifndef CONFIG_DM_ETH
fdt_fixup_board_phy(fdt);
+#endif
} else {
fdt_status_fail(fdt, offset);
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ u16 mc_memory_bank = 0;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank++;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the three GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
size[2] = gd->arch.resv_ram - base[2];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
#ifdef CONFIG_USB
fsl_fdt_fixup_dr_usb(blob, bd);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
return 0;
}
projects / oweals / u-boot.git / blobdiff