// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*
*/
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_DM_ETH
#define EMI_NONE 0
#define EMI1 1 /* Mdio Bus 1 */
#define EMI2 2 /* Mdio Bus 2 */
}
#endif
+#endif /* !CONFIG_DM_ETH */
int board_eth_init(bd_t *bis)
{
+#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET)
struct memac_mdio_info mdio_info;
struct memac_mdio_controller *regs;
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
+#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_PHY_AQUANTIA
/*
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
+
+#ifdef CONFIG_DM_ETH
+ return 0;
+#else
return pci_eth_init(bis);
+#endif
}
#if defined(CONFIG_RESET_PHY_R)
}
#endif /* CONFIG_RESET_PHY_R */
+#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET)
int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
{
return offset;
}
+ phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
+ if (is_backplane_mode(phy_string)) {
+ /* Backplane KR mode: skip fixups */
+ printf("Interface %d in backplane KR mode\n", dpmac_id);
+ return 0;
+ }
+
ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
if (ret)
printf("%d@%s %d\n", __LINE__, __func__, ret);
return ret;
}
#endif // CONFIG_FSL_MC_ENET
-
+#endif