common: Move hang() to the same header as panic()

[oweals/u-boot.git] / board / freescale / ls1012ardb / ls1012ardb.c

diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 286f9d81995196b5d8852944ec7a97af35fa1c43..0f665c7bc68fa94445c14d7c05ab1532ddb5a22b 100644 (file)
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -1,10 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <fdt_support.h>
+#include <hang.h>
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -19,15 +20,19 @@
 #include <mmc.h>
 #include <scsi.h>
 #include <fsl_esdhc.h>
-#include <environment.h>
+#include <env_internal.h>
 #include <fsl_mmdc.h>
 #include <netdev.h>
 #include <fsl_sec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BOOT_FROM_UPPER_BANK   0x2
+#define BOOT_FROM_LOWER_BANK   0x1
+
 int checkboard(void)
 {
+#ifdef CONFIG_TARGET_LS1012ARDB
        u8 in1;
 
        puts("Board: LS1012ARDB ");
@@ -77,12 +82,26 @@ int checkboard(void)
                puts(": bank2\n");
        else
                puts("unknown\n");
+#else
 
+       puts("Board: LS1012A2G5RDB ");
+#endif
        return 0;
 }
 
+#ifdef CONFIG_TFABOOT
+int dram_init(void)
+{
+       gd->ram_size = tfa_get_dram_size();
+       if (!gd->ram_size)
+               gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
+#else
 int dram_init(void)
 {
+#ifndef CONFIG_TFABOOT
        static const struct fsl_mmdc_info mparam = {
                0x05180000,     /* mdctl */
                0x00030035,     /* mdpdc */
@@ -100,6 +119,7 @@ int dram_init(void)
        };
 
        mmdc_init(&mparam);
+#endif
 
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
@@ -109,11 +129,8 @@ int dram_init(void)
 
        return 0;
 }
+#endif
 
-int board_eth_init(bd_t *bis)
-{
-       return pci_eth_init(bis);
-}
 
 int board_early_init_f(void)
 {
@@ -130,7 +147,8 @@ int board_init(void)
         * Set CCI-400 control override register to enable barrier
         * transaction
         */
-       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+       if (current_el() == 3)
+               out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
        erratum_a010315();
@@ -150,6 +168,7 @@ int board_init(void)
        return 0;
 }
 
+#ifdef CONFIG_TARGET_LS1012ARDB
 int esdhc_status_fixup(void *blob, const char *compat)
 {
        char esdhc1_path[] = "/soc/esdhc@1580000";
@@ -193,7 +212,6 @@ int esdhc_status_fixup(void *blob, const char *compat)
                if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
                        sdhc2_en = true;
        }
-
        if (sdhc2_en)
                do_fixup_by_path(blob, esdhc1_path, "status", "okay",
                                 sizeof("okay"), 1);
@@ -202,6 +220,7 @@ int esdhc_status_fixup(void *blob, const char *compat)
                                 sizeof("disabled"), 1);
        return 0;
 }
+#endif
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
@@ -211,3 +230,85 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        return 0;
 }
+
+static int switch_to_bank1(void)
+{
+       u8 data;
+       int ret;
+
+       i2c_set_bus_num(0);
+
+       data = 0xf4;
+       ret = i2c_write(0x24, 0x3, 1, &data, 1);
+       if (ret) {
+               printf("i2c write error to chip : %u, addr : %u, data : %u\n",
+                      0x24, 0x3, data);
+       }
+
+       return ret;
+}
+
+static int switch_to_bank2(void)
+{
+       u8 data;
+       int ret;
+
+       i2c_set_bus_num(0);
+
+       data = 0xfc;
+       ret = i2c_write(0x24, 0x7, 1, &data, 1);
+       if (ret) {
+               printf("i2c write error to chip : %u, addr : %u, data : %u\n",
+                      0x24, 0x7, data);
+               goto err;
+       }
+
+       data = 0xf5;
+       ret = i2c_write(0x24, 0x3, 1, &data, 1);
+       if (ret) {
+               printf("i2c write error to chip : %u, addr : %u, data : %u\n",
+                      0x24, 0x3, data);
+       }
+err:
+       return ret;
+}
+
+static int convert_flash_bank(int bank)
+{
+       int ret = 0;
+
+       switch (bank) {
+       case BOOT_FROM_UPPER_BANK:
+               ret = switch_to_bank2();
+               break;
+       case BOOT_FROM_LOWER_BANK:
+               ret = switch_to_bank1();
+               break;
+       default:
+               ret = CMD_RET_USAGE;
+               break;
+       };
+
+       return ret;
+}
+
+static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+                         char * const argv[])
+{
+       if (argc != 2)
+               return CMD_RET_USAGE;
+       if (strcmp(argv[1], "1") == 0)
+               convert_flash_bank(BOOT_FROM_LOWER_BANK);
+       else if (strcmp(argv[1], "2") == 0)
+               convert_flash_bank(BOOT_FROM_UPPER_BANK);
+       else
+               return CMD_RET_USAGE;
+
+       return 0;
+}
+
+U_BOOT_CMD(
+       boot_bank, 2, 0, flash_bank_cmd,
+       "Flash bank Selection Control",
+       "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
+);