Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / board / Marvell / db-mv784mp-gp / db-mv784mp-gp.c

diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
index 00ca878873d92a807a92a5af7778119eb80609c5..63bb771ab3c978fa3036d2136aa2c31c63a8ec5c 100644 (file)
--- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
@@ -1,19 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <init.h>
 #include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
+#include <linux/bitops.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define BIT(nr)                                (1UL << (nr))
-
 #define ETH_PHY_CTRL_REG               0
 #define ETH_PHY_CTRL_POWER_DOWN_BIT    11
 #define ETH_PHY_CTRL_POWER_DOWN_MASK   (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
@@ -82,40 +83,38 @@ int checkboard(void)
        return 0;
 }
 
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1545 PHY */
-void reset_phy(void)
+int board_eth_init(bd_t *bis)
 {
-       u8 phy_addr[] = CONFIG_PHY_ADDR;
-       u16 devadr = phy_addr[0];
-       char *name = "neta0";
-       u16 reg;
+       cpu_eth_init(bis); /* Built in controller(s) come first */
+       return pci_eth_init(bis);
+}
 
-       if (miiphy_set_current_dev(name))
-               return;
+int board_phy_config(struct phy_device *phydev)
+{
+       u16 reg;
 
        /* Enable QSGMII AN */
        /* Set page to 4 */
-       miiphy_write(name, devadr, 0x16, 4);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
        /* Enable AN */
-       miiphy_write(name, devadr, 0x0, 0x1140);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
        /* Set page to 0 */
-       miiphy_write(name, devadr, 0x16, 0);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
 
        /* Phy C_ANEG */
-       miiphy_read(name, devadr, 0x4, &reg);
+       reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
        reg |= 0x1E0;
-       miiphy_write(name, devadr, 0x4, reg);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
 
        /* Soft-Reset */
-       miiphy_write(name, devadr, 22, 0x0000);
-       miiphy_write(name, devadr, 0, 0x9140);
+       phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
 
        /* Power up the phy */
-       miiphy_read(name, devadr, ETH_PHY_CTRL_REG, &reg);
+       reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
        reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
-       miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg);
+       phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
 
-       printf("88E1545 Initialized on %s\n", name);
+       printf("88E1545 Initialized\n");
+       return 0;
 }
-#endif /* CONFIG_RESET_PHY_R */