Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / board / CarMediaLab / flea3 / flea3.c

diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
index 2463077475ace1cb1aecefe3557bd12fac77f3b9..61d965f5f65ac6963f379c3a7be8956a28106658 100644 (file)
--- a/board/CarMediaLab/flea3/flea3.c
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -1,15 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  *
  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <init.h>
 #include <asm/io.h>
+#include <env.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
@@ -19,6 +21,9 @@
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
 #include <netdev.h>
+#include <fdt_support.h>
+#include <mtd_node.h>
+#include <jffs2/load_kernel.h>
 
 #ifndef CONFIG_BOARD_EARLY_INIT_F
 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
@@ -27,18 +32,6 @@
 #define CCM_CCMR_CONFIG                0x003F4208
 
 #define ESDCTL_DDR2_CONFIG     0x007FFC3F
-#define ESDCTL_0x92220000      0x92220000
-#define ESDCTL_0xA2220000      0xA2220000
-#define ESDCTL_0xB2220000      0xB2220000
-#define ESDCTL_0x82228080      0x82228080
-#define ESDCTL_DDR2_EMR2       0x04000000
-#define ESDCTL_DDR2_EMR3       0x06000000
-#define ESDCTL_PRECHARGE       0x00000400
-#define ESDCTL_DDR2_EN_DLL     0x02000400
-#define ESDCTL_DDR2_RESET_DLL  0x00000333
-#define ESDCTL_DDR2_MR         0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-#define ESDCTL_DELAY_LINE5     0x00F49F00
 
 static inline void dram_wait(unsigned int count)
 {
@@ -58,83 +51,6 @@ int dram_init(void)
        return 0;
 }
 
-static void board_setup_sdram_bank(u32 start_address)
-
-{
-       struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-       u32 *cfg_reg, *ctl_reg;
-       u32 val;
-
-       switch (start_address) {
-       case CSD0_BASE_ADDR:
-               cfg_reg = &esdc->esdcfg0;
-               ctl_reg = &esdc->esdctl0;
-               break;
-       case CSD1_BASE_ADDR:
-               cfg_reg = &esdc->esdcfg1;
-               ctl_reg = &esdc->esdctl1;
-               break;
-       default:
-               return;
-       }
-
-       /* Initialize MISC register for DDR2 */
-       val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
-               ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
-       writel(val, &esdc->esdmisc);
-       val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
-       writel(val, &esdc->esdmisc);
-
-       /*
-        * according to DDR2 specs, wait a while before
-        * the PRECHARGE_ALL command
-        */
-       dram_wait(0x20000);
-
-       /* Load DDR2 config and timing */
-       writel(ESDCTL_DDR2_CONFIG, cfg_reg);
-
-       /* Precharge ALL */
-       writel(ESDCTL_0x92220000,
-               ctl_reg);
-       writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-       /* Load mode */
-       writel(ESDCTL_0xB2220000,
-               ctl_reg);
-       writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
-       writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
-       writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-       writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
-
-       /* Precharge ALL */
-       writel(ESDCTL_0x92220000,
-               ctl_reg);
-       writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-       /* Set mode auto refresh : at least two refresh are required */
-       writel(ESDCTL_0xA2220000,
-               ctl_reg);
-       writel(0xda, start_address);
-       writel(0xda, start_address);
-
-       writel(ESDCTL_0xB2220000,
-               ctl_reg);
-       writeb(0xda, start_address + ESDCTL_DDR2_MR);
-       writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
-
-       /* OCD mode exit */
-       writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-
-       /* Set normal mode */
-       writel(ESDCTL_0x82228080,
-               ctl_reg);
-
-       dram_wait(0x20000);
-
-       /* Do not set delay lines, only for MDDR */
-}
-
 static void board_setup_sdram(void)
 {
        struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
@@ -143,7 +59,9 @@ static void board_setup_sdram(void)
        writel(0x2000, &esdc->esdctl0);
        writel(0x2000, &esdc->esdctl1);
 
-       board_setup_sdram_bank(CSD0_BASE_ADDR);
+
+       mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+                            13, 10, 2, 0x8080);
 }
 
 static void setup_iomux_uart3(void)
@@ -206,6 +124,8 @@ static void setup_iomux_fec(void)
                MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
                MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
                MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+               /* GPIO used to power off ethernet */
+               MX35_PAD_STXFS4__GPIO2_31,
        };
 
        /* setup pins for FEC */
@@ -267,6 +187,11 @@ int board_init(void)
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+       /* Enable power for ethernet */
+       gpio_direction_output(63, 0);
+
+       udelay(2000);
+
        return 0;
 }
 
@@ -276,3 +201,24 @@ u32 get_board_rev(void)
 
        return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 }
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ */
+int ft_board_setup(void *blob, bd_t *bd)
+{
+       static const struct node_info nodes[] = {
+               { "physmap-flash.0", MTD_DEV_TYPE_NOR, },  /* NOR flash */
+               { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+       };
+
+       if (env_get("fdt_noauto")) {
+               puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
+               return 0;
+       }
+
+       fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+       return 0;
+}