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Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...
[oweals/u-boot.git]
/
arch
/
x86
/
include
/
asm
/
arch-baytrail
/
acpi
/
southcluster.asl
diff --git
a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
index e89ff26f75f81dc49d4750a73c59aaad5a7dd5cf..3b220c7ac284fc764b01fd6f430ac7fcf356b6b0 100644
(file)
--- a/
arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
+++ b/
arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@
-1,10
+1,9
@@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
/*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
Device (PCI0)
*/
Device (PCI0)
@@
-12,7
+11,7
@@
Device (PCI0)
Name(_HID, EISAID("PNP0A08")) /* PCIe */
Name(_CID, EISAID("PNP0A03")) /* PCI */
Name(_HID, EISAID("PNP0A08")) /* PCIe */
Name(_CID, EISAID("PNP0A03")) /* PCI */
- Name(_
ADR
, 0)
+ Name(_
UID
, 0)
Name(_BBN, 0)
Name(MCRS, ResourceTemplate()
Name(_BBN, 0)
Name(MCRS, ResourceTemplate()
@@
-151,9
+150,9
@@
Device (PCI0)
CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
- /* Set base address to
48GB and allocate 16
GB for PCI space */
- Store(0x
c
00000000, UMIN)
- Store(0x
4
00000000, ULEN)
+ /* Set base address to
16GB and allocate 48
GB for PCI space */
+ Store(0x
4
00000000, UMIN)
+ Store(0x
c
00000000, ULEN)
Add(UMIN, Subtract(ULEN, 1), UMAX)
Return (MCRS)
Add(UMIN, Subtract(ULEN, 1), UMAX)
Return (MCRS)