Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / x86 / cpu / queensbay / tnc.c

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 933d189f05e23819c24502f02448f126be832316..782ed863fe7c7038fc70bf9377f2ee6fe27abd68 100644 (file)
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -1,30 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <dm/device-internal.h>
+#include <pci.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/arch/device.h>
 #include <asm/arch/tnc.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 #include <asm/processor.h>
 
-static void unprotect_spi_flash(void)
+static int __maybe_unused disable_igd(void)
 {
-       u32 bc;
+       struct udevice *igd, *sdvo;
+       int ret;
 
-       bc = x86_pci_read_config32(TNC_LPC, 0xd8);
-       bc |= 0x1;      /* unprotect the flash */
-       x86_pci_write_config32(TNC_LPC, 0xd8, bc);
-}
+       ret = dm_pci_bus_find_bdf(TNC_IGD, &igd);
+       if (ret)
+               return ret;
+       if (!igd)
+               return 0;
+
+       ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
+       if (ret)
+               return ret;
+       if (!sdvo)
+               return 0;
 
-static void __maybe_unused disable_igd(void)
-{
        /*
         * According to Atom E6xx datasheet, setting VGA Disable (bit17)
         * of Graphics Controller register (offset 0x50) prevents IGD
@@ -43,41 +51,60 @@ static void __maybe_unused disable_igd(void)
         * two devices will be completely disabled (invisible in the PCI
         * configuration space) unless a system reset is performed.
         */
-       x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE);
-       x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE);
-}
+       dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
+       dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
 
-int arch_cpu_init(void)
-{
-       int ret;
-
-       post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
-       timer_set_base(rdtsc());
-#endif
-
-       ret = x86_cpu_init_f();
+       /*
+        * After setting the function disable bit, IGD and SDVO devices will
+        * disappear in the PCI configuration space. This however creates an
+        * inconsistent state from a driver model PCI controller point of view,
+        * as these two PCI devices are still attached to its parent's child
+        * device list as maintained by the driver model. Some driver model PCI
+        * APIs like dm_pci_find_class(), are referring to the list to speed up
+        * the finding process instead of re-enumerating the whole PCI bus, so
+        * it gets the stale cached data which is wrong.
+        *
+        * Note x86 PCI enueration normally happens twice, in pre-relocation
+        * phase and post-relocation. One option might be to call disable_igd()
+        * in one of the pre-relocation initialization hooks so that it gets
+        * disabled in the first round, and when it comes to the second round
+        * driver model PCI will construct a correct list. Unfortunately this
+        * does not work as Intel FSP is used on this platform to perform low
+        * level initialization, and fsp_init_phase_pci() is called only once
+        * in the post-relocation phase. If we disable IGD and SDVO devices,
+        * fsp_init_phase_pci() simply hangs and never returns.
+        *
+        * So the only option we have is to manually remove these two devices.
+        */
+       ret = device_remove(igd, DM_REMOVE_NORMAL);
+       if (ret)
+               return ret;
+       ret = device_unbind(igd);
+       if (ret)
+               return ret;
+       ret = device_remove(sdvo, DM_REMOVE_NORMAL);
+       if (ret)
+               return ret;
+       ret = device_unbind(sdvo);
        if (ret)
                return ret;
 
        return 0;
 }
 
-int arch_early_init_r(void)
+int arch_cpu_init(void)
 {
-#ifdef CONFIG_DISABLE_IGD
-       disable_igd();
-#endif
+       post_code(POST_CPU_INIT);
 
-       return 0;
+       return x86_cpu_init_f();
 }
 
-void cpu_irq_init(void)
+static void tnc_irq_init(void)
 {
        struct tnc_rcba *rcba;
        u32 base;
 
-       base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
+       pci_read_config32(TNC_LPC, LPC_RCBA, &base);
        base &= ~MEM_BAR_EN;
        rcba = (struct tnc_rcba *)base;
 
@@ -109,9 +136,15 @@ void cpu_irq_init(void)
        writew(PIRQD, &rcba->d26ir);
 }
 
-int arch_misc_init(void)
+int arch_early_init_r(void)
 {
-       unprotect_spi_flash();
+       int ret = 0;
+
+#ifdef CONFIG_DISABLE_IGD
+       ret = disable_igd();
+#endif
+
+       tnc_irq_init();
 
-       return pirq_init();
+       return ret;
 }